SRAM

[Austin Semiconductor, Inc.] GENERAL DESCRIPTION The AS5C4009LL is organized as 524,288 x 8 SRAM utilizing a special ultra low power design process. ASI’s pinout adheres to the JEDEC standard for pinout on 4 megabit SRAMs. The evolutionary 32 pin version allows for easy upgrades from the 1 meg S

Three state outputs

GENERAL DESCRIPTION The AS5C4009 is organized as 524,288 x 8 SRAM utilizing a special ultra low power design process. Micross’ pinout adheres to the JEDEC standard for pinout on 4 megabit SRAMs. The evolutionary 32 pin version allows for easy upgrades from the 1 meg SRAM design. FEATURES • Ultr

SRAM

[Austin Semiconductor, Inc.] GENERAL DESCRIPTION The AS5C4009LL is organized as 524,288 x 8 SRAM utilizing a special ultra low power design process. ASI’s pinout adheres to the JEDEC standard for pinout on 4 megabit SRAMs. The evolutionary 32 pin version allows for easy upgrades from the 1 meg S

Three state outputs

GENERAL DESCRIPTION The AS5C4009 is organized as 524,288 x 8 SRAM utilizing a special ultra low power design process. Micross’ pinout adheres to the JEDEC standard for pinout on 4 megabit SRAMs. The evolutionary 32 pin version allows for easy upgrades from the 1 meg SRAM design. FEATURES • Ultr