DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP

DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP TheSN54LS/74LS73A offers individual J, K, clear, and clock inputs.These dualflip-flops aredesigned so that when the clock goes HIGH, the inputs are enabledand data will be accepted. The logic level of the J and K inputs may beallowed to change when the

DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP

DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP TheSN54LS/74LS73A offers individual J, K, clear, and clock inputs.These dualflip-flops aredesigned so that when the clock goes HIGH, the inputs are enabledand data will be accepted. The logic level of the J and K inputs may beallowed to change when the

DUAL J-K FLIP-FLOPS WITH CLEAR

文件：206.08 Kbytes Page：13 Pages

DUAL J-K FLIP-FLOPS WITH CLEAR

文件：206.08 Kbytes Page：13 Pages

DUAL J-K FLIP-FLOPS WITH CLEAR

文件：206.08 Kbytes Page：13 Pages