Dual Positive-Edge-Triggered J-K Flip-Flops with Preset, Clear, and Complementary Outputs

General Description\nThis device contains two independent positive-edge-triggered J-K flip-flops with complementary outputs. The J and K data is accepted by the flip-flop on the rising edge of the clock pulse. The triggering occurs at a voltage level and is not directly related to the transition tim ■ Alternate Military/Aerospace device (54LS109) is available. Contact a National Semiconductor Sales Office/Distributor for specifications;

双J-K触发器（带预置和清零）

Dual Positive-Edge-Triggered J-K Flip-Flops with Preset, Clear, and Complementary Outputs

文件：135 Kbytes Page：6 Pages

Dual Positive-Edge-Triggered J-K Flip-Flops with Preset, Clear, and Complementary Outputs

文件：135 Kbytes Page：6 Pages

Dual Positive-Edge-Triggered J-K Flip-Flops with Preset, Clear, and Complementary Outputs

Dual Positive-Edge-Triggered J-K Flip-Flops with Preset, Clear, and Complementary Outputs

文件：135 Kbytes Page：6 Pages

Dual Positive-Edge-Triggered J-K Flip-Flops with Preset, Clear, and Complementary Outputs

文件：135 Kbytes Page：6 Pages

DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP

DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP LOW POWER SCHOTTKY The SN54/74LS109A consists of two high speed completely independent transition clocked JKflip-flops. The clocking operation is independent of rise andfall times of the clock waveform. The JKdesignallows operation as a D flip-flop by

Dual Positive-Edge-Triggered J-K Flip-Flops with Preset, Clear, and Complementary Outputs

文件：135 Kbytes Page：6 Pages

Dual Positive-Edge-Triggered J-K Flip-Flops with Preset, Clear, and Complementary Outputs

文件：135 Kbytes Page：6 Pages

Dual Positive-Edge-Triggered J-K Flip-Flops with Preset, Clear, and Complementary Outputs

文件：135 Kbytes Page：6 Pages