64BIT RANDOM ACCESS MEMORY

DESCRIPTION The 289 is a high speed 64-bit RAM organized as a 16-word by 4-bit array. Address input are buffered to minimize loading, and addresses are fully decoded on-chip.

Hex Inverters with Schmitt Trigger Inputs

文件：123.11 Kbytes Page：6 Pages

64BIT RANDOM ACCESS MEMORY

DUAL JK FLIP - FLOP

[Signetics]

The ’90 is a 4-stage ripple counter containing a high speed flip-flop acting as a divide-by-two and three flip-flops connected as a divideby- five counter.

DESCRIPTION — The ’90 is a 4-stage ripple counter containing a high speed flip-flop acting as a divide-by-two and three flip-flops connected as a divideby- five counter. It can be connected to operate with a conventional BCD output pattern or it can be connected to provide a 50 duty cycle outpu

QUAD 2-INPUT NAND GATE

QUAD 2-INPUT NAND GATES

QUAD 2-INPUT NAND GATE

QUAD 2-INPUT NAND GATES

QUAD 2-INPUT NAND GATE

QUAD 2-INPUT NAND GATES

HEX INVERTER

HEX INVERTER LOW POWER SCHOTTKY

Low Power Schottky Logic

Features: High speed – 19ns (Typ) propagation delay Full Military Temperature Range. Direct drop-in replacement for obsolete components in long term programs.

Low Power Schottky Logic

Features: High speed – 19ns (Typ) propagation delay Full Military Temperature Range. Direct drop-in replacement for obsolete components in long term programs.

TRIPLE 3-INPUT AND GATE

TRIPLE 3-INPUT AND GATE

TRIPLE 3-INPUT AND GATE

TRIPLE 3-INPUT AND GATE

TRIPLE 3-INPUT AND GATE

TRIPLE 3-INPUT AND GATE

RETRIGGERABLE MONOSTABLE MULTIVIBRATORS

These dc triggered multivibrators feature pulse width control by three methods. The basic pulse width is programmed by selection of external resistance and capacitance values. The LS122 has an internal timing resistor that allows the circuits to be used with only an external capacitor. Once trigge

QUAD 3-STATE BUFFERS

QUAD 3-STATE BUFFERS LOW POWER SCHOTTKY

1-OF-8 DECODER/ DEMULTIPLEXER

The LSTTL/MSI SN54/74LS138 is a high speed 1-of-8 Decoder/Demultiplexer. This device is ideally suited for high speed bipolar memory chip select address decoding. The multiple input enables allow parallel ex pansion to a 1-of-24 decoder using just three LS138 devices or to a 1-of-32 decoder using

Low Power Schottky Logic

Features: Demultiplexing capability Multiple Input Enables for parallel expansion Active Low Mutually Exclusive Outputs Input Clamp Diodes Limit High Speed Termination Effects Full Military Temperature Range. Direct drop-in replacement for obsolete components in long term programs.

Low Power Schottky Logic

Features: Demultiplexing capability Multiple Input Enables for parallel expansion Active Low Mutually Exclusive Outputs Input Clamp Diodes Limit High Speed Termination Effects Full Military Temperature Range. Direct drop-in replacement for obsolete components in long term programs.

Hex Inverter with Schmitt Trigger Inputs

General Description This device contains six independent gates each of which performs the logic INVERT function. Each input has hysteresis which increases the noise immunity and transforms a slowly changing input signal to a fast changing, jitter free output. Supply Voltage 7V Input Voltage 7V

TRIPLE 3-INPUT AND GATE

TRIPLE 3-INPUT AND GATE LOW POWER SCHOTTKY

8-INPUT MULTIPLEXER

The TTL /MSI SN54 /74LS151 is a high speed8-input Digital Multiplexer. Itprovides, in one package, the ability to select one bit of data from up to eight sources.The LS151 can be used as a universalfunction generator to generateany logic function of four variables. Bothassertion and negation outpu

Low Power Schottky Logic

Features: Aysnchronous Master Reset Gated Serial Data Input Fully Synchronous Data Transfers Direct drop-in replacement for obsolete components in long term programs. Full Military Temperature Range.

Low Power Schottky Logic

Features: Aysnchronous Master Reset Gated Serial Data Input Fully Synchronous Data Transfers Direct drop-in replacement for obsolete components in long term programs. Full Military Temperature Range.

4 X 4 REGISTER FILE (With Open-Collector Output)

DESCRIPTION The 170 contains 16 high speed, low power, transparent D-type latches arranged as four words of four bits each, to function as a 4 X 4 register file. Separate read and write inputs, both address and enable, allow simultaneous read and write operation.

4 X 4 REGISTER FILE (With Open-Collector Output)

DESCRIPTION The 170 contains 16 high speed, low power, transparent D-type latches arranged as four words of four bits each, to function as a 4 X 4 register file. Separate read and write inputs, both address and enable, allow simultaneous read and write operation.

Quad 2-Input NAND Gates

文件：120.38 Kbytes Page：6 Pages

Quad 2-Input NAND Gates

文件：120.38 Kbytes Page：6 Pages

Quad 2-Input NAND Gates

文件：120.38 Kbytes Page：6 Pages

Quad 2-Input NAND Gates

文件：120.38 Kbytes Page：6 Pages

Quad 2-Input NAND Gates

文件：120.38 Kbytes Page：6 Pages

Quad 2-Input NAND Gates

文件：120.38 Kbytes Page：6 Pages

四2输入与非门（OC）

四2输入或非门

Quad 2-Input NOR Gates

文件：120.07 Kbytes Page：6 Pages

Quad 2-Input NOR Gates

文件：120.07 Kbytes Page：6 Pages

Quad 2-Input NOR Gates

文件：120.07 Kbytes Page：6 Pages

Quad 2-Input NOR Gates

文件：120.07 Kbytes Page：6 Pages

Quad 2-Input NOR Gates

文件：120.07 Kbytes Page：6 Pages

Quad 2-Input NOR Gates

文件：120.07 Kbytes Page：6 Pages

Hex Inverting Gates

文件：120.24 Kbytes Page：6 Pages

These devices contain six independent inverters

文件：241.33 Kbytes Page：7 Pages

Low Power Schottky Logic

文件：435.7 Kbytes Page：4 Pages

Low Power Schottky Logic

文件：331.04 Kbytes Page：4 Pages

Hex Inverting Gates

文件：120.24 Kbytes Page：6 Pages

Hex Inverting Gates

文件：120.24 Kbytes Page：6 Pages

Hex Inverting Gates

文件：120.24 Kbytes Page：6 Pages

Hex Inverting Gates

文件：120.24 Kbytes Page：6 Pages

Hex Inverting Gates

文件：120.24 Kbytes Page：6 Pages

HEX INVERTERS WITH OPEN-COLLECTOR OUTPUTS

文件：61.25 Kbytes Page：2 Pages

HEX INVERTERS WITH OPEN-COLLECTOR OUTPUTS

文件：61.25 Kbytes Page：2 Pages

HEX INVERTERS WITH OPEN-COLLECTOR OUTPUTS

文件：61.25 Kbytes Page：2 Pages

Quad 2-Input AND Gates

文件：124.5 Kbytes Page：6 Pages

Quad 2-Input AND Gates

文件：124.5 Kbytes Page：6 Pages

Quad 2-Input AND Gates

文件：124.5 Kbytes Page：6 Pages

Quad 2-Input AND Gates

文件：124.5 Kbytes Page：6 Pages

Quad 2-Input AND Gates

文件：124.5 Kbytes Page：6 Pages

Quad 2-Input AND Gates

文件：124.5 Kbytes Page：6 Pages

QUAD 2-INPUT AND GATES WITH OPEN-COLLECTOR OUTPUTS

文件：61.29 Kbytes Page：2 Pages

QUAD 2-INPUT AND GATES WITH OPEN-COLLECTOR OUTPUTS

文件：61.29 Kbytes Page：2 Pages