64BIT RANDOM ACCESS MEMORY

DESCRIPTION The 289 is a high speed 64-bit RAM organized as a 16-word by 4-bit array. Address input are buffered to minimize loading, and addresses are fully decoded on-chip.

Hex Inverters with Schmitt Trigger Inputs

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DUAL JK FLIP - FLOP

[Signetics]

The ’90 is a 4-stage ripple counter containing a high speed flip-flop acting as a divide-by-two and three flip-flops connected as a divideby- five counter.

DESCRIPTION — The ’90 is a 4-stage ripple counter containing a high speed flip-flop acting as a divide-by-two and three flip-flops connected as a divideby- five counter. It can be connected to operate with a conventional BCD output pattern or it can be connected to provide a 50 duty cycle outpu

QUAD 2-INPUT NAND GATE

QUAD 2-INPUT NAND GATES

QUAD 2-INPUT NAND GATE

QUAD 2-INPUT NAND GATES

QUAD 2-INPUT NAND GATE

QUAD 2-INPUT NAND GATES

HEX INVERTER

HEX INVERTER LOW POWER SCHOTTKY

Low Power Schottky Logic

Features: High speed – 19ns (Typ) propagation delay Full Military Temperature Range. Direct drop-in replacement for obsolete components in long term programs.

Low Power Schottky Logic

Features: High speed – 19ns (Typ) propagation delay Full Military Temperature Range. Direct drop-in replacement for obsolete components in long term programs.

TRIPLE 3-INPUT AND GATE

TRIPLE 3-INPUT AND GATE

TRIPLE 3-INPUT AND GATE

TRIPLE 3-INPUT AND GATE

TRIPLE 3-INPUT AND GATE

TRIPLE 3-INPUT AND GATE

RETRIGGERABLE MONOSTABLE MULTIVIBRATORS

These dc triggered multivibrators feature pulse width control by three methods. The basic pulse width is programmed by selection of external resistance and capacitance values. The LS122 has an internal timing resistor that allows the circuits to be used with only an external capacitor. Once trigge

QUAD 3-STATE BUFFERS

QUAD 3-STATE BUFFERS LOW POWER SCHOTTKY

Low Power Schottky Logic

Features: Demultiplexing capability Multiple Input Enables for parallel expansion Active Low Mutually Exclusive Outputs Input Clamp Diodes Limit High Speed Termination Effects Full Military Temperature Range. Direct drop-in replacement for obsolete components in long term programs.

1-OF-8 DECODER/ DEMULTIPLEXER

The LSTTL/MSI SN54/74LS138 is a high speed 1-of-8 Decoder/Demultiplexer. This device is ideally suited for high speed bipolar memory chip select address decoding. The multiple input enables allow parallel ex pansion to a 1-of-24 decoder using just three LS138 devices or to a 1-of-32 decoder using

Low Power Schottky Logic

Features: Demultiplexing capability Multiple Input Enables for parallel expansion Active Low Mutually Exclusive Outputs Input Clamp Diodes Limit High Speed Termination Effects Full Military Temperature Range. Direct drop-in replacement for obsolete components in long term programs.

Hex Inverter with Schmitt Trigger Inputs

General Description This device contains six independent gates each of which performs the logic INVERT function. Each input has hysteresis which increases the noise immunity and transforms a slowly changing input signal to a fast changing, jitter free output. Supply Voltage 7V Input Voltage 7V

TRIPLE 3-INPUT AND GATE

TRIPLE 3-INPUT AND GATE LOW POWER SCHOTTKY

8-INPUT MULTIPLEXER

The TTL /MSI SN54 /74LS151 is a high speed8-input Digital Multiplexer. Itprovides, in one package, the ability to select one bit of data from up to eight sources.The LS151 can be used as a universalfunction generator to generateany logic function of four variables. Bothassertion and negation outpu

Low Power Schottky Logic

Features: Aysnchronous Master Reset Gated Serial Data Input Fully Synchronous Data Transfers Direct drop-in replacement for obsolete components in long term programs. Full Military Temperature Range.

Low Power Schottky Logic

Features: Aysnchronous Master Reset Gated Serial Data Input Fully Synchronous Data Transfers Direct drop-in replacement for obsolete components in long term programs. Full Military Temperature Range.

4 X 4 REGISTER FILE (With Open-Collector Output)

DESCRIPTION The 170 contains 16 high speed, low power, transparent D-type latches arranged as four words of four bits each, to function as a 4 X 4 register file. Separate read and write inputs, both address and enable, allow simultaneous read and write operation.

4 X 4 REGISTER FILE (With Open-Collector Output)

DESCRIPTION The 170 contains 16 high speed, low power, transparent D-type latches arranged as four words of four bits each, to function as a 4 X 4 register file. Separate read and write inputs, both address and enable, allow simultaneous read and write operation.

4 X 4 REGISTER FILE (With Open-Collector Output)

DESCRIPTION The 170 contains 16 high speed, low power, transparent D-type latches arranged as four words of four bits each, to function as a 4 X 4 register file. Separate read and write inputs, both address and enable, allow simultaneous read and write operation.

PRESETTABLE BCD/DECADE UP/DOWN COUNTER PRESETTABLE 4-BIT BINARY UP/DOWN COUNTER

TheSN54/74LS192 is an UP/DOWN BCD Decade (8421) Counter and the SN54/74LS193 is an UP/DOWN MODULO-16 Binary Counter. Separate CountUp and Count Down Clocks are used and in either counting mode the circuits operate synchronously. The outputs change state synchronous with the LOW-to-HIGH transitions

4-STAGE PRESETTABLE RIPPLE COUNTERS

4-STAGE PRESETTABLE RIPPLE COUNTERS The SN54/74LS196 decade counter is partitioned into divide-by-two and divide-by-five sections which can be combined to count either in BCD (8, 4, 2, 1) sequence or in a bi-quinary mode producing a 50 duty cycle output. The SN54/74LS197 contains divide-by-tw

4-STAGE PRESETTABLE RIPPLE COUNTERS

4-STAGE PRESETTABLE RIPPLE COUNTERS The SN54/74LS196 decade counter is partitioned into divide-by-two and divide-by-five sections which can be combined to count either in BCD (8, 4, 2, 1) sequence or in a bi-quinary mode producing a 50 duty cycle output. The SN54/74LS197 contains divide-by-tw

DUAL 4-INPUT POSITIVE AND GATE

DUAL 4-INPUT POSITIVE AND GATE

DUAL 4-INPUT POSITIVE AND GATE

DUAL 4-INPUT POSITIVE AND GATE

DUAL 4-INPUT POSITIVE AND GATE

DUAL 4-INPUT POSITIVE AND GATE

QUAD 2-INPUT MULTIPLEXER WITH 3-STATE OUTPUTS

QUAD 2-INPUT MULTIPLEXER WITH 3-STATE OUTPUTS The LSTTL/MSI SN54/74LS257B and the SN54/74LS258B are Quad 2-Input Multiplexers with 3-state outputs. Four bits of data from two sources can be selected using a Common Data Select input. The four outputs present the selected data in true (non-inverted

DUAL 5-INPUT NOR GATE

DUAL 5-INPUT NOR GATE

TRIPLE 3-INPUT NOR GATE

TRIPLE 3-INPUT NOR GATE

TRIPLE 3-INPUT NOR GATE

TRIPLE 3-INPUT NOR GATE

TRIPLE 3-INPUT NOR GATE

TRIPLE 3-INPUT NOR GATE

BCD TO 7-SEGMENT DECODER/DRIVER

DESCRIPTION The 347 is the same as the 47 except that the Output OFF Voltage, VOH, is specified as 7.0 V rather than 15 V, with the same IOH litmit of 250 μA. For all other information please refer to the 47 data sheet.

BCD TO 7-SEGMENT DECODER/DRIVER

DESCRIPTION The 347 is the same as the 47 except that the Output OFF Voltage, VOH, is specified as 7.0 V rather than 15 V, with the same IOH litmit of 250 μA. For all other information please refer to the 47 data sheet.

BCD TO 7-SEGMENT DECODER/DRIVER

DESCRIPTION The 347 is the same as the 47 except that the Output OFF Voltage, VOH, is specified as 7.0 V rather than 15 V, with the same IOH litmit of 250 μA. For all other information please refer to the 47 data sheet.

DUAL 4-INPUT NAND BUFFER

DUAL 4-INPUT NAND BUFFER LOW POWER SCHOTTKY

DUAL JK FLIP - FLOP

[Signetics]

4-BIT BINARY FULL ADDER

DESCRIPTION The 83A high speed 4-bit binary full adders with internal carry lookahead accept two 4-bin binary words (A0-A3, B0-B3) and a Carry input (C0).

4-BIT BINARY FULL ADDER

DESCRIPTION The 83A high speed 4-bit binary full adders with internal carry lookahead accept two 4-bin binary words (A0-A3, B0-B3) and a Carry input (C0).

4-BIT BINARY FULL ADDER

DESCRIPTION The 83A high speed 4-bit binary full adders with internal carry lookahead accept two 4-bin binary words (A0-A3, B0-B3) and a Carry input (C0).

Low Power Schottky Logic

Features: High speed – 22ns (Typ) propagation delay Low Power – ICC 10mA Max Full Military Temperature Range. Direct drop-in replacement for obsolete components in long term programs.

Low Power Schottky Logic

Features: High speed – 22ns (Typ) propagation delay Low Power – ICC 10mA Max Full Military Temperature Range. Direct drop-in replacement for obsolete components in long term programs.

64-Bit Random Access Memory(Open Collector)

DESCRIPTION The 89 is a 64-Bit high-speed Read/Write Random Access Memory for use as a scratch pad memory with non-destructive read-out. Memory cells are organized in a matrix to provide 16 words of four bits each.

The ’90 is a 4-stage ripple counter containing a high speed flip-flop acting as a divide-by-two and three flip-flops connected as a divideby- five counter.

DESCRIPTION — The ’90 is a 4-stage ripple counter containing a high speed flip-flop acting as a divide-by-two and three flip-flops connected as a divideby- five counter. It can be connected to operate with a conventional BCD output pattern or it can be connected to provide a 50 duty cycle outpu

The ’90 is a 4-stage ripple counter containing a high speed flip-flop acting as a divide-by-two and three flip-flops connected as a divideby- five counter.

DESCRIPTION — The ’90 is a 4-stage ripple counter containing a high speed flip-flop acting as a divide-by-two and three flip-flops connected as a divideby- five counter. It can be connected to operate with a conventional BCD output pattern or it can be connected to provide a 50 duty cycle outpu

The ’90 is a 4-stage ripple counter containing a high speed flip-flop acting as a divide-by-two and three flip-flops connected as a divideby- five counter.

DESCRIPTION — The ’90 is a 4-stage ripple counter containing a high speed flip-flop acting as a divide-by-two and three flip-flops connected as a divideby- five counter. It can be connected to operate with a conventional BCD output pattern or it can be connected to provide a 50 duty cycle outpu

DIVIDE-BY-TWELVE COUNTER

DESCRIPTION- The ’92 is a 4-stage ripple counter containing a high speed flip-flop acting as a divide-by-two and three flip-flops connected as a divide-by-six. HIGH signals on the Master Reset (MR) inputs override the clocks and force all outputs to the LOW state.

DIVIDE-BY-TWELVE COUNTER

DESCRIPTION- The ’92 is a 4-stage ripple counter containing a high speed flip-flop acting as a divide-by-two and three flip-flops connected as a divide-by-six. HIGH signals on the Master Reset (MR) inputs override the clocks and force all outputs to the LOW state.

4-BIT RIGHT/LEFT SHIGT REGISTER

DUAL JK FLIP - FLOP

[Signetics]

The ’90 is a 4-stage ripple counter containing a high speed flip-flop acting as a divide-by-two and three flip-flops connected as a divideby- five counter.

DESCRIPTION — The ’90 is a 4-stage ripple counter containing a high speed flip-flop acting as a divide-by-two and three flip-flops connected as a divideby- five counter. It can be connected to operate with a conventional BCD output pattern or it can be connected to provide a 50% duty cycle

Quad 2-Input NAND Gates

文件：120.38 Kbytes Page：6 Pages

Quad 2-Input NAND Gates

文件：120.38 Kbytes Page：6 Pages

Quad 2-Input NAND Gates

文件：120.38 Kbytes Page：6 Pages

Quad 2-Input NAND Gates

文件：120.38 Kbytes Page：6 Pages