High Speed CMOS Logic Dual 4-Stage Static Shift Register

Features • Maximum Frequency, Typically 60MHz CL = 15pF, VCC = 5V, TA = 25oC • Positive-Edge Clocking • Overriding Reset • Buffered Inputs and Outputs • Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . .

High Speed CMOS Logic Dual 4-Stage Static Shift Register

Features • Maximum Frequency, Typically 60MHz CL = 15pF, VCC = 5V, TA = 25oC • Positive-Edge Clocking • Overriding Reset • Buffered Inputs and Outputs • Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . .

High Speed CMOS Logic Dual 4-Stage Static Shift Register

文件：260.149 Kbytes Page：5 Pages

High Speed CMOS Logic Dual 4-Stage Static Shift Register

文件：266.08 Kbytes Page：10 Pages

High Speed CMOS Logic Dual 4-Stage Static Shift Register

文件：377.67 Kbytes Page：11 Pages