3MScotch-WeldMetalInstantAdhesiveMC100

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8-BITSYNCHRONOUSBINARYUPCOUNTER

Description TheMC10E/100E016isahigh−speedsynchronous,presettable,cascadable8−bitbinarycounter.ArchitectureandoperationarethesameastheMC10H016intheMECL10H™family,extendedto8−bits,asshowninthelogicsymbol. Features •700MHzMin.CountFrequency •1000psCLK

QUAD4-INPUTOR/NORGATE

TheMC10E/100E101isaquad4-inputOR/NORgate. •500psMax.PropagationDelay •Extended100EVEERangeof–4.2Vto–5.46V •75kΩInputPulldownResistors

5VECLQuad4짯InputOR/NORGate

Description TheMC10E/100E101isaquad4-inputOR/NORgate. The100Seriescontainstemperaturecompensation. Features •500psMax.PropagationDelay •PECLModeOperatingRange: VCC=4.2Vto5.7VwithVEE=0V •NECLModeOperatingRange: VCC=0VwithVEE=−4.2Vto−5.7

5VECLQuad4짯InputOR/NORGate

Description TheMC10E/100E101isaquad4-inputOR/NORgate. The100Seriescontainstemperaturecompensation. Features •500psMax.PropagationDelay •PECLModeOperatingRange: VCC=4.2Vto5.7VwithVEE=0V •NECLModeOperatingRange: VCC=0VwithVEE=−4.2Vto−5.7

5VECLQuad4짯InputOR/NORGate

Description TheMC10E/100E101isaquad4-inputOR/NORgate. The100Seriescontainstemperaturecompensation. Features •500psMax.PropagationDelay •PECLModeOperatingRange: VCC=4.2Vto5.7VwithVEE=0V •NECLModeOperatingRange: VCC=0VwithVEE=−4.2Vto−5.7

QUINT2-INPUTAND/NANDGATE

Description TheMC10E/100E104isaquint2-inputAND/NANDgate.ThefunctionoutputFistheORofallfiveANDgateoutputs,whileFistheNOR.TheQoutputsneednotbeterminatedifonlytheFoutputsaretobeused.The100Seriescontainstemperaturecompensation. Features •600psMax.P

QUINT2-INPUTXOR/XNORGATE

Description TheMC10E/100E107isaquint2-inputXOR/XNORgate.ThefunctionoutputFistheORofallfiveXORoutputs,whileFistheNOR.TheQoutputsneednotbeterminatedifonlytheFoutputsaretobeused. The100Seriescontainstemperaturecompensation. Features •600psMaximumPr

1:9DIFFERENTIALCLOCKDRIVER

Description TheMC10E/100E111isalowskew1-to-9differentialdriver,designedwithclockdistributioninmind.Itacceptsonesignalinput,whichcanbeeitherdifferentialorelsesingle-endediftheVBBoutputisused.Thesignalisfannedoutto9identicaldifferentialoutputs.Anenablei

QUADDRIVER

Description TheMC10E/100E112isaquaddriverwithtwopairsofOR/NORoutputsfromeachgate,andacommon,bufferedenableinput.UsingthedatainputsthedevicecanserveasanECLmemoryaddressfan-outdriver.Usingjusttheenableinput,thedeviceservesasaclockdriver,althoughtheM

QUINTDIFFERENTIALLINERECEIVER

Description TheMC10E/100E116isaquintdifferentiallinereceiverwithemitter-followeroutputs.ForapplicationswhichrequirebandwidthsgreaterthanthatoftheE116,theE416devicemaybeofinterest. ActivecurrentsourcesplusadeepcollectorfeatureoftheMOSAICIIIprocessprovidet

9-BITBUFFER

Description TheMC10E/100E122isa9-bitbuffer.Thedevicecontainsninenon-invertingbuffergates. The100Seriescontainstemperaturecompensation. Features •500psMax.PropagationDelay •PECLModeOperatingRange:VCC=4.2Vto5.7VwithVEE=0V •NECLModeOperatingRange:VCC=

4-BITDFLIP-FLOP

Description TheMC10E/100E131isaquadmaster-slaveD-typeflip-flopwithdifferentialoutputs.Eachflip-flopmaybeclockedseparatelybyholdingCommonClock(CC)LOWandusingtheClockEnable(CE)inputsforclocking.CommonclockingisachievedbyholdingtheCEinputsLOWandusingCCto

6-BITUNIVERSALUP/DOWNCOUNTER

Description TheMC10E/100E136isa6-bitsynchronous,presettable,cascadableuniversalcounter.Thedevicegeneratesalook-ahead-carryoutputandacceptsalook-ahead-carryinput.ThesetwofeaturesallowforthecascadingofmultipleE136’sforwiderbitwidthcountersthatoperateatverynea

8-BITRIPPLECOUNTER

Description TheMC10E/100E137isaveryhighspeedbinaryripplecounter.ThetwoleastsignificantbitsweredesignedwithveryfastedgerateswhilethemoresignificantbitsmaintainstandardECLinPS™outputedgerates.Thisallowsthecountertooperateatveryhighfrequencieswhilemaintain

8-BITSHIFTREGISTER

Description TheMC10E/100E141isan8-bitfull-functionshiftregister.TheE141performsserial/parallelinandserial/parallelout,shiftingineitherdirection.TheeightinputsD0−D7acceptparallelinputdata,whileDL/DRacceptserialinputdataforleft/rightshifting.TheQnoutputsdo

9-BITSHIFTREGISTER

Description TheMC10E/100E142isa9-bitshiftregister,designedwithbyte-parityapplicationsinmind.TheE142performsserial/parallelinandserial/parallelout,shiftinginonedirection.ThenineinputsD0−D8acceptparallelinputdata,whileS-INacceptsserialinputdata.TheQnoutput

9-BITHOLDREGISTER

Description TheMC10E/100E143isa9-bitholdingregister,designedwithbyte-parityapplicationsinmind.TheE143holdscurrentdataorloadsnewdata,withthenineinputsD0−D8acceptingparallelinputdata. TheSEL(Select)inputpinisusedtoswitchbetweenthetwomodesofoperation−

6-BITDLATCH

Description TheMC10E/100E150containssixD-typelatcheswithdifferentialoutputs.WhenbothLatchEnables(LEN1,LEN2)areLOW,thelatchistransparentandinputdatatransitionspropagatethroughtotheoutput.AlogicHIGHoneitherLEN1orLEN2(orboth)latchesthedata.TheMasterReset

6-BITDREGISTER

Description TheMC10E/100E151contains6D-type,edge-triggered,master-slaveflip-flopswithdifferentialoutputs.DataentersthemasterwhenbothCLK1andCLK2areLOW,andistransferredtotheslavewhenCLK1orCLK2(orboth)goHIGH.TheasynchronousMasterReset(MR)makesallQoutputsg

5-BIT2:1MUX-LATCH

Description TheMC10E/100E154containsfive2:1multiplexersfollowedbytransparentlatcheswithdifferentialoutputs.WhenbothLatchEnables(LEN1,LEN2)areLOW,thelatchistransparent,andoutputdataiscontrolledbythemultiplexerselectcontrol,SEL.AlogicHIGHoneitherLEN1orLEN2

5-BIT2:1MUX-LATCH

Description TheMC10E/100E154containsfive2:1multiplexersfollowedbytransparentlatcheswithdifferentialoutputs.WhenbothLatchEnables(LEN1,LEN2)areLOW,thelatchistransparent,andoutputdataiscontrolledbythemultiplexerselectcontrol,SEL.AlogicHIGHoneitherLEN1orLEN2

6-BIT2:1MUX-LATCH

Description TheMC10E/100E155containssix2:1multiplexersfollowedbytransparentlatcheswithsingle−endedoutputs.WhenbothLatchEnables(LEN1,LEN2)areLOW,thelatchistransparent,andoutputdataiscontrolledbythemultiplexerselectcontrol,SEL.AlogicHIGHoneitherLEN1orLEN2

3-BIT4:1MUX-LATCH

Description TheMC10E/100E156containsthree4:1multiplexersfollowedbytransparentlatcheswithdifferentialoutputs.WhenbothLatchEnables(LEN1,LEN2)areLOW,thelatchistransparent,andoutputdateiscontrolledbythemultiplexerselectcontrols(SEL0,SEL1).AlogicHIGHoneitherLE

QUAD2:1MULTIPLEXER

TheMC10E/100E157containsfour2:1multiplexerswithdifferentialoutputs.TheoutputdataarecontrolledbytheindividualSelect(SEL)inputs.Theindividualselectcontrolmakesthedeviceswellsuitedforrandomlogicdesigns. •IndividualSelectControls •550psMax.DtoOutput •80

QUAD2:1MULTIPLEXER

Description TheMC10E/100E157containsfour2:1multiplexerswithdifferentialoutputs.TheoutputdataarecontrolledbytheindividualSelect(SEL)inputs.Theindividualselectcontrolmakesthedeviceswellsuitedforrandomlogicdesigns. The100Seriescontainstemperaturecompensation.

QUAD2:1MULTIPLEXER

TheMC10E/100E157containsfour2:1multiplexerswithdifferentialoutputs.TheoutputdataarecontrolledbytheindividualSelect(SEL)inputs.Theindividualselectcontrolmakesthedeviceswellsuitedforrandomlogicdesigns. •IndividualSelectControls •550psMax.DtoOutput •80

QUAD2:1MULTIPLEXER

TheMC10E/100E157containsfour2:1multiplexerswithdifferentialoutputs.TheoutputdataarecontrolledbytheindividualSelect(SEL)inputs.Theindividualselectcontrolmakesthedeviceswellsuitedforrandomlogicdesigns. •IndividualSelectControls •550psMax.DtoOutput •80

5-BIT2:1MULTIPLEXER

Description TheMC10E/100E158containsfive2:1multiplexerswithdifferentialoutputs.TheoutputdataarecontrolledbytheSelectinput(SEL). The100Seriescontainstemperaturecompensation. Features •600psMax.DtoOutput •800psMax.SELtoOutput •DifferentialOutputs •OneVCC

12-BITPARITYGENERATOR/CHECKER

TheMC10E/100E160isa12-bitparitygenerator/checker.TheQoutputisHIGHwhenanoddnumberofinputsareHIGH.AHIGHontheEnableinput(EN)forcestheQoutputLOW. The100Seriescontainstemperaturecompensation. •ProvidesOdd-HIGHParityof12Inputs •ShiftableOutputRegisterwith

2-BIT8:1MULTIPLEXER

Description TheMC10E/100E163containstwo8:1multiplexerswithdifferentialoutputsandcommonselectinputs.Theselectinputs(SEL0,1,2)controlwhichoneoftheeightdatainputs(A0−A7,B0−B7)ispropagatedtotheoutput. The100Seriescontainstemperaturecompensation. Features •

16:1MULTIPLEXER

Description TheMC10E/100E164isa16:1multiplexerwithadifferentialoutput.Theselectinputs(SEL0,1,2,3)controlwhichoneofthesixteendatainputs(A0−A15)ispropagatedtotheoutput. Specialattentiontothedesignlayoutresultsinatypicalskewbetweenthe16inputsofonly5

9-BITMAGNITUDECOMPARATOR

Description TheMC10E/100E166isa9-bitmagnitudecomparatorwhichcomparesthebinaryvalueoftwo9-bitwordsandindicateswhetheronewordisgreaterthan,orequalto,theother. The100Seriescontainstemperaturecompensation Features •1100psMax.A=B •PECLModeOperatingRange:

6-BIT2:1MUX-REGISTER

Description TheMC10E/100E167containssix2:1multiplexersfollowedbyDflip-flopswithsingle-endedoutputs.InputdataareselectedbytheSelectcontrol,SEL.Theselecteddataaretransferredtotheflip-flopoutputsbyapositiveedgeonCLK1orCLK2(orboth).AHIGHontheMasterReset(

3-BIT4:1MULTIPLEXER

Description TheMC10E/100E171containsthree4:1multiplexerswithdifferentialoutputs.SeparateSelectcontrolsareprovidedfortheleading2:1MUXpairs(seelogicsymbol).ThethreeSelectinputscontrolwhichoneofthefourdatainputsineachcaseispropagatedtothecorrespondingoutput

9-BITLATCHWITHPARITY

Description TheMC10E/100E175isa9-bitlatch.Italsofeaturesatenthlatchedoutput,ODDPAR,whichisformedastheoddparityoftheninedatainputs(ODDPARisHIGHifanoddnumberoftheinputsareHIGH). TheE175canalsobeusedtogeneratebyteparitybyusingD8astheparity-typese

ERRORDETECTION/CORRECTIONCIRCUIT

TheMC10E/100E193isanerrordetectionandcorrection(EDAC)circuit.ModifiedHammingparitycodesaregeneratedonan8-bitwordaccordingtothepatternshowninthelogicsymbol.TheP5outputgivestheparityofthewholeword.ThewordparityisalsoprovidedatthePGENpin,afterOdd/Even

PROGRAMMABLEDELAYCHIP

Description TheMC10E/100E195isaprogrammabledelaychip(PDC)designedprimarilyforclockde-skewingandtimingadjustment.ItprovidesvariabledelayofadifferentialECLinputtransition. Thedelaysectionconsistsofachainofgatesorganizedasshowninthelogicsymbol.Thefirsttwo

PROGRAMMABLEDELAYCHIP

Description TheMC10E/100E196isaprogrammabledelaychip(PDC)designedprimarilyforveryaccuratedifferentialECLinputedgeplacementapplications. Thedelaysectionconsistsofachainofgatesandalinearrampdelayadjustorganizedasshowninthelogicsymbol.Thefirsttwodelayelem

5VECLDual1:4,1:5DifferentialFanoutBuffer

LowVoltageDual1:4,1:5DifferentialFanoutBufferECL/PECLCompatible TheMC100LVE210isalowvoltage,lowskewdualdifferentialECLfanoutbufferdesignedwithclockdistributioninmind.Thedevicefeaturestwofanoutbuffers,a1:4anda1:5buffer,onasinglechip.Thedevicefeaturesf

LowVoltageDual1:4,1:5DifferentialFanoutBuffer

LowVoltageDual1:4,1:5DifferentialFanoutBufferECL/PECLCompatible TheMC100LVE210isalowvoltage,lowskewdualdifferentialECLfanoutbufferdesignedwithclockdistributioninmind.Thedevicefeaturestwofanoutbuffers,a1:4anda1:5buffer,onasinglechip.Thedevicefeaturesf

5VECLDual1:4,1:5DifferentialFanoutBuffer

LowVoltageDual1:4,1:5DifferentialFanoutBufferECL/PECLCompatible TheMC100LVE210isalowvoltage,lowskewdualdifferentialECLfanoutbufferdesignedwithclockdistributioninmind.Thedevicefeaturestwofanoutbuffers,a1:4anda1:5buffer,onasinglechip.Thedevicefeaturesf

LowVoltageDual1:4,1:5DifferentialFanoutBuffer

LowVoltageDual1:4,1:5DifferentialFanoutBufferECL/PECLCompatible TheMC100LVE210isalowvoltage,lowskewdualdifferentialECLfanoutbufferdesignedwithclockdistributioninmind.Thedevicefeaturestwofanoutbuffers,a1:4anda1:5buffer,onasinglechip.Thedevicefeaturesf

5VECLDual1:4,1:5DifferentialFanoutBuffer

LowVoltageDual1:4,1:5DifferentialFanoutBufferECL/PECLCompatible TheMC100LVE210isalowvoltage,lowskewdualdifferentialECLfanoutbufferdesignedwithclockdistributioninmind.Thedevicefeaturestwofanoutbuffers,a1:4anda1:5buffer,onasinglechip.Thedevicefeaturesf

1:6DIFFERENTIALCLOCKDISTRIBUTIONCHIP

TheMC10E/100E211isalowskew1:6fanoutdevicedesignedexplicitlyforlowskewclockdistributionapplications. The100Seriescontainstemperaturecompensation. •GuaranteedLowSkewSpecification •SynchronousEnabling/Disabling •MultiplexedClockInputs •VBBOutputforSingle-EndedU

3-BITSCANNABLEREGISTEREDADDRESSDRIVER

TheMC10E/100E212isascannableregisteredECLdrivertypicallyusedasafan-outmemoryaddressdriverforECLcachedriving.InaVLSIarraybasedCPUdesign,useoftheE212allowstheusertoconservearrayoutputcellfunctionalityandalsooutputpins. Theinputshiftregisterisdesigned

8-BITSCANABLEREGISTER

5VECL8-BitScannableRegister TheMC10E/100E241isan8-bitshiftableregister.UnlikeastandarduniversalshiftregistersuchastheE141,theE241featuresinternaldatafeedbackorganizedsothattheSHIFTcontroloverridestheHOLD/LOADcontrol.ThisenablesthenormaloperationsofHOLDa

3-BIT4:1MUX-LATCH

TheMC10E/100E256containsthree4:1multiplexersfollowedbytransparentlatcheswithdifferentialoutputs.SeparateSelectcontrolsareprovidedfortheleading2:1muxpairs(seelogicsymbol). WhentheLatchEnable(LEN)isLOW,thelatchistransparent,andoutputdataiscontrolledbythem

5VECLLowVoltage2:8DifferentialFanoutBuffer

Description TheMC100E310isalowvoltage,lowskew2:8differentialECLfanoutbufferdesignedwithclockdistributioninmind.Thedevicefeaturesfullydifferentialclockpathstominimizebothdeviceandsystemskew.TheE310offerstwoselectableclockinputstoallowforredundantortest

5VECLLowVoltage2:8DifferentialFanoutBuffer

Description TheMC100E310isalowvoltage,lowskew2:8differentialECLfanoutbufferdesignedwithclockdistributioninmind.Thedevicefeaturesfullydifferentialclockpathstominimizebothdeviceandsystemskew.TheE310offerstwoselectableclockinputstoallowforredundantortest

5VECLLowVoltage2:8DifferentialFanoutBuffer

Description TheMC100E310isalowvoltage,lowskew2:8differentialECLfanoutbufferdesignedwithclockdistributioninmind.Thedevicefeaturesfullydifferentialclockpathstominimizebothdeviceandsystemskew.TheE310offerstwoselectableclockinputstoallowforredundantortest

5VECLLowVoltage2:8DifferentialFanoutBuffer

Description TheMC100E310isalowvoltage,lowskew2:8differentialECLfanoutbufferdesignedwithclockdistributioninmind.Thedevicefeaturesfullydifferentialclockpathstominimizebothdeviceandsystemskew.TheE310offerstwoselectableclockinputstoallowforredundantortest

5VECLLowVoltage2:8DifferentialFanoutBuffer

Description TheMC100E310isalowvoltage,lowskew2:8differentialECLfanoutbufferdesignedwithclockdistributioninmind.Thedevicefeaturesfullydifferentialclockpathstominimizebothdeviceandsystemskew.TheE310offerstwoselectableclockinputstoallowforredundantortest

3-BITREGISTEREDBUSTRANSCEIVER

TheMC10E/MC100E336containsthreebustransceiverswithbothtransmitandreceiveregisters.Thebusoutputs(BUS0–BUS2)arespecifiedfordrivinga25Ωbus;thereceiveoutputs(Q0–Q2)arespecifiedfor50Ω.ThebusoutputsfeatureanormalHIGHlevel(VOH)andacutoffLOWlevel—whenLOW,

3-BITSCANNABLEREGISTEREDBUSTRANSCEIVER

TheMC10E/100E337isa3-bitregisteredbustransceiverwithscan.Thebusoutputs(BUS0–BUS2)arespecifiedfordrivinga25Ωbus;thereceiveoutputs(Q0–Q2)arespecifiedfor50Ω.ThebusoutputsfeatureanormalHIGHlevel(VOH)andacutoffLOWlevel—whenLOW,theoutputsgoto–2.0V

QUADDIFFERENTIALAND/NAND

TheMC10E404/100E404isa4-bitdifferentialAND/NANDdevice.Thedifferentialoperationofthedevicemakesitidealforpulseshapingapplicationswheredutycycleskewiscritical.Specialdesigntechniqueswereincorporatedtominimizetheskewbetweentheupperandlowerlevelgateinputs. T

QUADDIFFERENTIALAND/NAND

TheMC10E404/100E404isa4-bitdifferentialAND/NANDdevice.Thedifferentialoperationofthedevicemakesitidealforpulseshapingapplicationswheredutycycleskewiscritical.Specialdesigntechniqueswereincorporatedtominimizetheskewbetweentheupperandlowerlevelgateinputs. T

QUADDIFFERENTIALAND/NAND

TheMC10E404/100E404isa4-bitdifferentialAND/NANDdevice.Thedifferentialoperationofthedevicemakesitidealforpulseshapingapplicationswheredutycycleskewiscritical.Specialdesigntechniqueswereincorporatedtominimizetheskewbetweentheupperandlowerlevelgateinputs. T

QUINTDIFFERENTIALLINERECEIVER

Description TheMC10E416/100E416isa5-bitdifferentiallinereceivingdevice.The2.0GHzofbandwidthprovidedbythehighfrequencyoutputsmakesthedeviceidealforbufferingofveryhighspeedoscillators. Thedesignincorporatestwostagesofgain,internaltothedevice,makingitanex

3-BITDIFFERENTIALFLIP-FLOP

Description TheMC10E/100E431isa3-bitflip-flopwithdifferentialclock,datainputanddataoutput. TheasynchronousSetandResetcontrolsareedge-triggeredratherthanlevelcontrolled.Thisallowstheusertorapidlysetorresettheflip-flopandthencontinueclockingatthenextclock