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型号 功能描述 生产厂家&企业 LOGO 操作
K4H510438

512MbB-dieDDRSDRAMSpecification

KeyFeatures •VDD:2.5V±0.2V,VDDQ:2.5V±0.2VforDDR266,333 •VDD:2.6V±0.1V,VDDQ:2.6V±0.1VforDDR400 •Double-data-ratearchitecture;twodatatransfersperclockcycle •Bidirectionaldatastrobe[DQS](x4,x8)&[L(U)DQS](x16) •Fourbanksoperation •Differentialcl

SamsungSamsung Group

三星三星半导体

Samsung
K4H510438A-TCA0

128MbDDRSDRAM

Features •Double-data-ratearchitecture;twodatatransfersperclockcycle •Bidirectionaldatastrobe(DQS) •Fourbanksoperation •Differentialclockinputs(CKandCK) •DLLalignsDQandDQStransitionwithCKtransition •MRScyclewithaddresskeyprograms -.Readlatency2,2.5(

SamsungSamsung Group

三星三星半导体

Samsung
K4H510438A-TCA2

128MbDDRSDRAM

Features •Double-data-ratearchitecture;twodatatransfersperclockcycle •Bidirectionaldatastrobe(DQS) •Fourbanksoperation •Differentialclockinputs(CKandCK) •DLLalignsDQandDQStransitionwithCKtransition •MRScyclewithaddresskeyprograms -.Readlatency2,2.5(

SamsungSamsung Group

三星三星半导体

Samsung
K4H510438A-TCB0

128MbDDRSDRAM

Features •Double-data-ratearchitecture;twodatatransfersperclockcycle •Bidirectionaldatastrobe(DQS) •Fourbanksoperation •Differentialclockinputs(CKandCK) •DLLalignsDQandDQStransitionwithCKtransition •MRScyclewithaddresskeyprograms -.Readlatency2,2.5(

SamsungSamsung Group

三星三星半导体

Samsung
K4H510438A-TLA0

128MbDDRSDRAM

Features •Double-data-ratearchitecture;twodatatransfersperclockcycle •Bidirectionaldatastrobe(DQS) •Fourbanksoperation •Differentialclockinputs(CKandCK) •DLLalignsDQandDQStransitionwithCKtransition •MRScyclewithaddresskeyprograms -.Readlatency2,2.5(

SamsungSamsung Group

三星三星半导体

Samsung
K4H510438A-TLA2

128MbDDRSDRAM

Features •Double-data-ratearchitecture;twodatatransfersperclockcycle •Bidirectionaldatastrobe(DQS) •Fourbanksoperation •Differentialclockinputs(CKandCK) •DLLalignsDQandDQStransitionwithCKtransition •MRScyclewithaddresskeyprograms -.Readlatency2,2.5(

SamsungSamsung Group

三星三星半导体

Samsung
K4H510438A-TLB0

128MbDDRSDRAM

Features •Double-data-ratearchitecture;twodatatransfersperclockcycle •Bidirectionaldatastrobe(DQS) •Fourbanksoperation •Differentialclockinputs(CKandCK) •DLLalignsDQandDQStransitionwithCKtransition •MRScyclewithaddresskeyprograms -.Readlatency2,2.5(

SamsungSamsung Group

三星三星半导体

Samsung
K4H510438B-TC/LA2

512MbB-dieDDRSDRAMSpecification

KeyFeatures •VDD:2.5V±0.2V,VDDQ:2.5V±0.2VforDDR266,333 •VDD:2.6V±0.1V,VDDQ:2.6V±0.1VforDDR400 •Double-data-ratearchitecture;twodatatransfersperclockcycle •Bidirectionaldatastrobe[DQS](x4,x8)&[L(U)DQS](x16) •Fourbanksoperation •Differentialcl

SamsungSamsung Group

三星三星半导体

Samsung
K4H510438B-TC/LB0

512MbB-dieDDRSDRAMSpecification

KeyFeatures •VDD:2.5V±0.2V,VDDQ:2.5V±0.2VforDDR266,333 •VDD:2.6V±0.1V,VDDQ:2.6V±0.1VforDDR400 •Double-data-ratearchitecture;twodatatransfersperclockcycle •Bidirectionaldatastrobe[DQS](x4,x8)&[L(U)DQS](x16) •Fourbanksoperation •Differentialcl

SamsungSamsung Group

三星三星半导体

Samsung
K4H510438B-TC/LB3

512MbB-dieDDRSDRAMSpecification

KeyFeatures •VDD:2.5V±0.2V,VDDQ:2.5V±0.2VforDDR266,333 •VDD:2.6V±0.1V,VDDQ:2.6V±0.1VforDDR400 •Double-data-ratearchitecture;twodatatransfersperclockcycle •Bidirectionaldatastrobe[DQS](x4,x8)&[L(U)DQS](x16) •Fourbanksoperation •Differentialcl

SamsungSamsung Group

三星三星半导体

Samsung
K4H510438B-TCA0

128MbDDRSDRAM

Features •Double-data-ratearchitecture;twodatatransfersperclockcycle •Bidirectionaldatastrobe(DQS) •Fourbanksoperation •Differentialclockinputs(CKandCK) •DLLalignsDQandDQStransitionwithCKtransition •MRScyclewithaddresskeyprograms -.Readlatency2,2.5(

SamsungSamsung Group

三星三星半导体

Samsung
K4H510438B-TCA2

128MbDDRSDRAM

Features •Double-data-ratearchitecture;twodatatransfersperclockcycle •Bidirectionaldatastrobe(DQS) •Fourbanksoperation •Differentialclockinputs(CKandCK) •DLLalignsDQandDQStransitionwithCKtransition •MRScyclewithaddresskeyprograms -.Readlatency2,2.5(

SamsungSamsung Group

三星三星半导体

Samsung
K4H510438B-TCB0

128MbDDRSDRAM

Features •Double-data-ratearchitecture;twodatatransfersperclockcycle •Bidirectionaldatastrobe(DQS) •Fourbanksoperation •Differentialclockinputs(CKandCK) •DLLalignsDQandDQStransitionwithCKtransition •MRScyclewithaddresskeyprograms -.Readlatency2,2.5(

SamsungSamsung Group

三星三星半导体

Samsung
K4H510438B-TLA0

128MbDDRSDRAM

Features •Double-data-ratearchitecture;twodatatransfersperclockcycle •Bidirectionaldatastrobe(DQS) •Fourbanksoperation •Differentialclockinputs(CKandCK) •DLLalignsDQandDQStransitionwithCKtransition •MRScyclewithaddresskeyprograms -.Readlatency2,2.5(

SamsungSamsung Group

三星三星半导体

Samsung
K4H510438B-TLA2

128MbDDRSDRAM

Features •Double-data-ratearchitecture;twodatatransfersperclockcycle •Bidirectionaldatastrobe(DQS) •Fourbanksoperation •Differentialclockinputs(CKandCK) •DLLalignsDQandDQStransitionwithCKtransition •MRScyclewithaddresskeyprograms -.Readlatency2,2.5(

SamsungSamsung Group

三星三星半导体

Samsung
K4H510438B-TLB0

128MbDDRSDRAM

Features •Double-data-ratearchitecture;twodatatransfersperclockcycle •Bidirectionaldatastrobe(DQS) •Fourbanksoperation •Differentialclockinputs(CKandCK) •DLLalignsDQandDQStransitionwithCKtransition •MRScyclewithaddresskeyprograms -.Readlatency2,2.5(

SamsungSamsung Group

三星三星半导体

Samsung
K4H510438B-UC/LA2

512MbB-dieDDRSDRAMSpecification

KeyFeatures •VDD:2.5V±0.2V,VDDQ:2.5V±0.2VforDDR266,333 •VDD:2.6V±0.1V,VDDQ:2.6V±0.1VforDDR400 •Double-data-ratearchitecture;twodatatransfersperclockcycle •Bidirectionaldatastrobe[DQS](x4,x8)&[L(U)DQS](x16) •Fourbanksoperation •Differentialcl

SamsungSamsung Group

三星三星半导体

Samsung
K4H510438B-UC/LB0

512MbB-dieDDRSDRAMSpecification

KeyFeatures •VDD:2.5V±0.2V,VDDQ:2.5V±0.2VforDDR266,333 •VDD:2.6V±0.1V,VDDQ:2.6V±0.1VforDDR400 •Double-data-ratearchitecture;twodatatransfersperclockcycle •Bidirectionaldatastrobe[DQS](x4,x8)&[L(U)DQS](x16) •Fourbanksoperation •Differentialcl

SamsungSamsung Group

三星三星半导体

Samsung
K4H510438B-UC/LB3

512MbB-dieDDRSDRAMSpecification

KeyFeatures •VDD:2.5V±0.2V,VDDQ:2.5V±0.2VforDDR266,333 •VDD:2.6V±0.1V,VDDQ:2.6V±0.1VforDDR400 •Double-data-ratearchitecture;twodatatransfersperclockcycle •Bidirectionaldatastrobe[DQS](x4,x8)&[L(U)DQS](x16) •Fourbanksoperation •Differentialcl

SamsungSamsung Group

三星三星半导体

Samsung
K4H510438C-TCA0

128MbDDRSDRAM

Features •Double-data-ratearchitecture;twodatatransfersperclockcycle •Bidirectionaldatastrobe(DQS) •Fourbanksoperation •Differentialclockinputs(CKandCK) •DLLalignsDQandDQStransitionwithCKtransition •MRScyclewithaddresskeyprograms -.Readlatency2,2.5(

SamsungSamsung Group

三星三星半导体

Samsung
K4H510438C-TCA2

128MbDDRSDRAM

Features •Double-data-ratearchitecture;twodatatransfersperclockcycle •Bidirectionaldatastrobe(DQS) •Fourbanksoperation •Differentialclockinputs(CKandCK) •DLLalignsDQandDQStransitionwithCKtransition •MRScyclewithaddresskeyprograms -.Readlatency2,2.5(

SamsungSamsung Group

三星三星半导体

Samsung
K4H510438C-TCB0

128MbDDRSDRAM

Features •Double-data-ratearchitecture;twodatatransfersperclockcycle •Bidirectionaldatastrobe(DQS) •Fourbanksoperation •Differentialclockinputs(CKandCK) •DLLalignsDQandDQStransitionwithCKtransition •MRScyclewithaddresskeyprograms -.Readlatency2,2.5(

SamsungSamsung Group

三星三星半导体

Samsung
K4H510438C-TLA0

128MbDDRSDRAM

Features •Double-data-ratearchitecture;twodatatransfersperclockcycle •Bidirectionaldatastrobe(DQS) •Fourbanksoperation •Differentialclockinputs(CKandCK) •DLLalignsDQandDQStransitionwithCKtransition •MRScyclewithaddresskeyprograms -.Readlatency2,2.5(

SamsungSamsung Group

三星三星半导体

Samsung
K4H510438C-TLA2

128MbDDRSDRAM

Features •Double-data-ratearchitecture;twodatatransfersperclockcycle •Bidirectionaldatastrobe(DQS) •Fourbanksoperation •Differentialclockinputs(CKandCK) •DLLalignsDQandDQStransitionwithCKtransition •MRScyclewithaddresskeyprograms -.Readlatency2,2.5(

SamsungSamsung Group

三星三星半导体

Samsung
K4H510438C-TLB0

128MbDDRSDRAM

Features •Double-data-ratearchitecture;twodatatransfersperclockcycle •Bidirectionaldatastrobe(DQS) •Fourbanksoperation •Differentialclockinputs(CKandCK) •DLLalignsDQandDQStransitionwithCKtransition •MRScyclewithaddresskeyprograms -.Readlatency2,2.5(

SamsungSamsung Group

三星三星半导体

Samsung
K4H510438D

DDRSDRAMProductGuide

ConsumerMemory

SamsungSamsung Group

三星三星半导体

Samsung
K4H510438D

512MbD-dieDDRSDRAMSpecification

KeyFeatures •VDD:2.5V±0.2V,VDDQ:2.5V±0.2VforDDR266,333 •VDD:2.6V±0.1V,VDDQ:2.6V±0.1VforDDR400 •Double-data-ratearchitecture;twodatatransfersperclockcycle •Bidirectionaldatastrobe[DQS](x4,x8)&[L(U)DQS](x16) •Fourbanksoperation •Dif

SamsungSamsung Group

三星三星半导体

Samsung
K4H510438D-TCA0

128MbDDRSDRAM

Features •Double-data-ratearchitecture;twodatatransfersperclockcycle •Bidirectionaldatastrobe(DQS) •Fourbanksoperation •Differentialclockinputs(CKandCK) •DLLalignsDQandDQStransitionwithCKtransition •MRScyclewithaddresskeyprograms -.Readlatency2,2.5(

SamsungSamsung Group

三星三星半导体

Samsung
K4H510438D-TCA2

128MbDDRSDRAM

Features •Double-data-ratearchitecture;twodatatransfersperclockcycle •Bidirectionaldatastrobe(DQS) •Fourbanksoperation •Differentialclockinputs(CKandCK) •DLLalignsDQandDQStransitionwithCKtransition •MRScyclewithaddresskeyprograms -.Readlatency2,2.5(

SamsungSamsung Group

三星三星半导体

Samsung
K4H510438D-TCB0

128MbDDRSDRAM

Features •Double-data-ratearchitecture;twodatatransfersperclockcycle •Bidirectionaldatastrobe(DQS) •Fourbanksoperation •Differentialclockinputs(CKandCK) •DLLalignsDQandDQStransitionwithCKtransition •MRScyclewithaddresskeyprograms -.Readlatency2,2.5(

SamsungSamsung Group

三星三星半导体

Samsung
K4H510438D-TLA0

128MbDDRSDRAM

Features •Double-data-ratearchitecture;twodatatransfersperclockcycle •Bidirectionaldatastrobe(DQS) •Fourbanksoperation •Differentialclockinputs(CKandCK) •DLLalignsDQandDQStransitionwithCKtransition •MRScyclewithaddresskeyprograms -.Readlatency2,2.5(

SamsungSamsung Group

三星三星半导体

Samsung
K4H510438D-TLA2

128MbDDRSDRAM

Features •Double-data-ratearchitecture;twodatatransfersperclockcycle •Bidirectionaldatastrobe(DQS) •Fourbanksoperation •Differentialclockinputs(CKandCK) •DLLalignsDQandDQStransitionwithCKtransition •MRScyclewithaddresskeyprograms -.Readlatency2,2.5(

SamsungSamsung Group

三星三星半导体

Samsung
K4H510438D-TLB0

128MbDDRSDRAM

Features •Double-data-ratearchitecture;twodatatransfersperclockcycle •Bidirectionaldatastrobe(DQS) •Fourbanksoperation •Differentialclockinputs(CKandCK) •DLLalignsDQandDQStransitionwithCKtransition •MRScyclewithaddresskeyprograms -.Readlatency2,2.5(

SamsungSamsung Group

三星三星半导体

Samsung
K4H510438D-UC/LA2

512MbD-dieDDRSDRAMSpecification

KeyFeatures •VDD:2.5V±0.2V,VDDQ:2.5V±0.2VforDDR266,333 •VDD:2.6V±0.1V,VDDQ:2.6V±0.1VforDDR400 •Double-data-ratearchitecture;twodatatransfersperclockcycle •Bidirectionaldatastrobe[DQS](x4,x8)&[L(U)DQS](x16) •Fourbanksoperation •Dif

SamsungSamsung Group

三星三星半导体

Samsung
K4H510438D-UC/LB0

512MbD-dieDDRSDRAMSpecification

KeyFeatures •VDD:2.5V±0.2V,VDDQ:2.5V±0.2VforDDR266,333 •VDD:2.6V±0.1V,VDDQ:2.6V±0.1VforDDR400 •Double-data-ratearchitecture;twodatatransfersperclockcycle •Bidirectionaldatastrobe[DQS](x4,x8)&[L(U)DQS](x16) •Fourbanksoperation •Dif

SamsungSamsung Group

三星三星半导体

Samsung
K4H510438E-TCA0

128MbDDRSDRAM

Features •Double-data-ratearchitecture;twodatatransfersperclockcycle •Bidirectionaldatastrobe(DQS) •Fourbanksoperation •Differentialclockinputs(CKandCK) •DLLalignsDQandDQStransitionwithCKtransition •MRScyclewithaddresskeyprograms -.Readlatency2,2.5(

SamsungSamsung Group

三星三星半导体

Samsung
K4H510438E-TCA2

128MbDDRSDRAM

Features •Double-data-ratearchitecture;twodatatransfersperclockcycle •Bidirectionaldatastrobe(DQS) •Fourbanksoperation •Differentialclockinputs(CKandCK) •DLLalignsDQandDQStransitionwithCKtransition •MRScyclewithaddresskeyprograms -.Readlatency2,2.5(

SamsungSamsung Group

三星三星半导体

Samsung
K4H510438E-TCB0

128MbDDRSDRAM

Features •Double-data-ratearchitecture;twodatatransfersperclockcycle •Bidirectionaldatastrobe(DQS) •Fourbanksoperation •Differentialclockinputs(CKandCK) •DLLalignsDQandDQStransitionwithCKtransition •MRScyclewithaddresskeyprograms -.Readlatency2,2.5(

SamsungSamsung Group

三星三星半导体

Samsung
K4H510438E-TLA0

128MbDDRSDRAM

Features •Double-data-ratearchitecture;twodatatransfersperclockcycle •Bidirectionaldatastrobe(DQS) •Fourbanksoperation •Differentialclockinputs(CKandCK) •DLLalignsDQandDQStransitionwithCKtransition •MRScyclewithaddresskeyprograms -.Readlatency2,2.5(

SamsungSamsung Group

三星三星半导体

Samsung
K4H510438E-TLA2

128MbDDRSDRAM

Features •Double-data-ratearchitecture;twodatatransfersperclockcycle •Bidirectionaldatastrobe(DQS) •Fourbanksoperation •Differentialclockinputs(CKandCK) •DLLalignsDQandDQStransitionwithCKtransition •MRScyclewithaddresskeyprograms -.Readlatency2,2.5(

SamsungSamsung Group

三星三星半导体

Samsung
K4H510438E-TLB0

128MbDDRSDRAM

Features •Double-data-ratearchitecture;twodatatransfersperclockcycle •Bidirectionaldatastrobe(DQS) •Fourbanksoperation •Differentialclockinputs(CKandCK) •DLLalignsDQandDQStransitionwithCKtransition •MRScyclewithaddresskeyprograms -.Readlatency2,2.5(

SamsungSamsung Group

三星三星半导体

Samsung
K4H510438F

ConsumerMemory

SDRAMProductGuide MemoryDivision November2007

SamsungSamsung Group

三星三星半导体

Samsung
K4H510438F

512MbF-dieDDRSDRAMSpecification

ConsumerMemory

SamsungSamsung Group

三星三星半导体

Samsung
K4H510438F-LC/LB0

512MbF-dieDDRSDRAMSpecification

ConsumerMemory

SamsungSamsung Group

三星三星半导体

Samsung
K4H510438F-LC/LB3

512MbF-dieDDRSDRAMSpecification

ConsumerMemory

SamsungSamsung Group

三星三星半导体

Samsung
K4H510438G

512MbG-dieDDRSDRAMSpecification

GeneralDescription TheK4H510438G/K4H510838G/K4H511638Gis536,870,912bitsofdoubledataratesynchronousDRAMorganizedas4x33,554,432/4x16,777,216/4x8,388,608wordsby4/8/16bits,fabricatedwithSAMSUNG′shighperformanceCMOStechnology.SynchronousfeatureswithDataStrobeal

SamsungSamsung Group

三星三星半导体

Samsung
K4H510438G

ConsumerMemory

SDRAMProductGuide MemoryDivision November2007

SamsungSamsung Group

三星三星半导体

Samsung
K4H510438G-LC/LB0

512MbG-dieDDRSDRAMSpecification

GeneralDescription TheK4H510438G/K4H510838G/K4H511638Gis536,870,912bitsofdoubledataratesynchronousDRAMorganizedas4x33,554,432/4x16,777,216/4x8,388,608wordsby4/8/16bits,fabricatedwithSAMSUNG′shighperformanceCMOStechnology.SynchronousfeatureswithDataStrobeal

SamsungSamsung Group

三星三星半导体

Samsung
K4H510438G-LC/LB3

512MbG-dieDDRSDRAMSpecification

GeneralDescription TheK4H510438G/K4H510838G/K4H511638Gis536,870,912bitsofdoubledataratesynchronousDRAMorganizedas4x33,554,432/4x16,777,216/4x8,388,608wordsby4/8/16bits,fabricatedwithSAMSUNG′shighperformanceCMOStechnology.SynchronousfeatureswithDataStrobeal

SamsungSamsung Group

三星三星半导体

Samsung
K4H510438M-TCA0

128MbDDRSDRAM

Features •Double-data-ratearchitecture;twodatatransfersperclockcycle •Bidirectionaldatastrobe(DQS) •Fourbanksoperation •Differentialclockinputs(CKandCK) •DLLalignsDQandDQStransitionwithCKtransition •MRScyclewithaddresskeyprograms -.Readlatency2,2.5(

SamsungSamsung Group

三星三星半导体

Samsung
K4H510438M-TCA2

128MbDDRSDRAM

Features •Double-data-ratearchitecture;twodatatransfersperclockcycle •Bidirectionaldatastrobe(DQS) •Fourbanksoperation •Differentialclockinputs(CKandCK) •DLLalignsDQandDQStransitionwithCKtransition •MRScyclewithaddresskeyprograms -.Readlatency2,2.5(

SamsungSamsung Group

三星三星半导体

Samsung
K4H510438M-TCB0

128MbDDRSDRAM

Features •Double-data-ratearchitecture;twodatatransfersperclockcycle •Bidirectionaldatastrobe(DQS) •Fourbanksoperation •Differentialclockinputs(CKandCK) •DLLalignsDQandDQStransitionwithCKtransition •MRScyclewithaddresskeyprograms -.Readlatency2,2.5(

SamsungSamsung Group

三星三星半导体

Samsung
K4H510438M-TLA0

128MbDDRSDRAM

Features •Double-data-ratearchitecture;twodatatransfersperclockcycle •Bidirectionaldatastrobe(DQS) •Fourbanksoperation •Differentialclockinputs(CKandCK) •DLLalignsDQandDQStransitionwithCKtransition •MRScyclewithaddresskeyprograms -.Readlatency2,2.5(

SamsungSamsung Group

三星三星半导体

Samsung
K4H510438M-TLA2

128MbDDRSDRAM

Features •Double-data-ratearchitecture;twodatatransfersperclockcycle •Bidirectionaldatastrobe(DQS) •Fourbanksoperation •Differentialclockinputs(CKandCK) •DLLalignsDQandDQStransitionwithCKtransition •MRScyclewithaddresskeyprograms -.Readlatency2,2.5(

SamsungSamsung Group

三星三星半导体

Samsung
K4H510438M-TLB0

128MbDDRSDRAM

Features •Double-data-ratearchitecture;twodatatransfersperclockcycle •Bidirectionaldatastrobe(DQS) •Fourbanksoperation •Differentialclockinputs(CKandCK) •DLLalignsDQandDQStransitionwithCKtransition •MRScyclewithaddresskeyprograms -.Readlatency2,2.5(

SamsungSamsung Group

三星三星半导体

Samsung
K4H510438B-GC/LA2

512MbB-dieDDRSDRAMSpecification

文件：392.89 Kbytes Page：24 Pages

SamsungSamsung Group

三星三星半导体

Samsung
K4H510438B-GC/LB0

512MbB-dieDDRSDRAMSpecification

文件：392.89 Kbytes Page：24 Pages

SamsungSamsung Group

三星三星半导体

Samsung
K4H510438B-GC/LB3

512MbB-dieDDRSDRAMSpecification

文件：392.89 Kbytes Page：24 Pages

SamsungSamsung Group

三星三星半导体

Samsung
K4H510438B-GC/LCC

512MbB-dieDDRSDRAMSpecification

文件：392.89 Kbytes Page：24 Pages

SamsungSamsung Group

三星三星半导体

Samsung
K4H510438B-ZC/LA2

512MbB-dieDDRSDRAMSpecification

文件：392.89 Kbytes Page：24 Pages

SamsungSamsung Group

三星三星半导体

Samsung

K4H510438产品属性

  • 类型

    描述

  • 型号

    K4H510438

  • 制造商

    SAMSUNG

  • 制造商全称

    Samsung semiconductor

  • 功能描述

    512Mb B-die DDR SDRAM Specification

K4H510438供应商更多...

更新时间：2024-5-13 15:19:00
IC供应商 芯片型号 品牌 批号 封装 库存 备注 价格
深圳市兴灿科技有限公司
K4H510438G-LCB3
SAMSUNG/三星
23+
TSOP-66
25500
授权代理直销,原厂原装现货,假一罚十,特价销售
询价
深圳市杰顺创科技有限公司
K4H510438B-GCB3
SAMSUNG/三星
19+
BGA
12606
进口原装现货
询价
深圳市宇创芯科技有限公司
K4H510438G-HCCC
SAMSUNG/三星
22+
FBGA
9600
原装现货,优势供应,支持实单!
询价
深圳市新力诚科技有限公司
K4H510438C-UCB3
SAMSUNG
2020+
原厂封装
3328
专营军工航天芯片,只做全新原装,价格超低!
询价
深圳市华来深电子有限公司
K4H510438F-HCCC
SAMSUNG
23+
FBGAP/
8560
受权代理!全新原装现货特价热卖!
询价
深圳市近平电子有限公司
K4H510438C-UCB3000
SAMSUNG
6000
面议
19
DIP/SMD
询价
深圳市晨豪科技有限公司
K4H510438G-LCB3
SAMSUNG/三星
23+
TSOP-66
89630
当天发货全新原装现货
询价
深圳诚思涵科技有限公司
K4H510438C-ZCCC
SAMSUNG
18+
FBGA60
85600
保证进口原装可开17%增值税发票
询价
深圳市胜彬电子有限公司
K4H510438G-LCB3
SAMSUNG
22+
TSOP-66
8000
原装正品支持实单
询价
深圳市赛美科科技有限公司
K4H510438G-HCB3
Samsung
ROHS
56520
一级代理 原装正品假一罚十价格优势长期供货
询价

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