Dual4-bitstaticshiftregister

DESCRIPTION TheHEF4015Bisadualedge-triggered4-bitstaticshiftregister(serial-to-parallelconverter).Eachshiftregisterhasaserialdatainput(D),aclockinput(CP),fourfullybufferedparalleloutputs(O0toO3)andanoverridingasynchronousmasterresetinput(MR).Informationpr

CMOSDual4-StageStaticShiftRegisterWithSerialInput/ParallelOutput

Description CD4015BMSconsistsoftwoidentical,independent,4-stageserial-input/paralleloutputregisters.EachregisterhasindependentCLOCKandRESETinputsaswellasasingleserialDATAinput.“Q”outputsareavailablefromeachofthefourstagesonbothregisters.Allregisterstages

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compactandeconomicalsurface-acousticwave(SAW)filter

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4-Bit Latched/4-to-16 Line Decoders

4-Bit Latched/4-to-16 Line Decoders

4-Bit Latched/4-to-16 Line Decoders

CMOS 4-BIT LATCH/4-TO-16 LINE DECODERS

CMOS 4-BIT LATCH/4-TO-16 LINE DECODERS

CMOS 4-BIT LATCH/4-TO-16 LINE DECODERS

4-Bit Latched/4-to-16 Line Decoders

Dual 4-bit static shift register

1-of-16 decoder/demultiplexer with input latches

4-Bit Transparent Latch/4-to-16 Line Decoder

4−Bit Transparent Latch / 4−to−16 Line Decoder

4-Bit Transparent Latch/4-to-16 Line Decoder

4-Bit Transparent Latch/4-to-16 Line Decoder

4−Bit Transparent Latch / 4−to−16 Line Decoder

CMOS 4-TO-16 LINE DECODERS WITH LATCH

CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC