H5P价格

参考价格:¥18.2543

型号:H5PS1G63KFR-S5C 品牌:SK Hynix 备注:这里有H5P多少钱,2024年最近7天走势,今日出价,今日竞价,H5P批发/采购报价,H5P行情走势销售排行榜,H5P报价。
型号 功能描述 生产厂家&企业 LOGO 操作
H5P

10/100 BASE-T FIVE PORT MAGNETICS

文件:332.71 Kbytes Page:2 Pages

BOTHHAND

Bothhand USA

BOTHHAND

1Gb DDR2 SDRAM

Description DeviceFeatures&OrderingInformation KeyFeatures •VDD=1.8+/-0.1V •VDDQ=1.8+/-0.1V •AllinputsandoutputsarecompatiblewithSSTL_18interface •8banks •Fullydifferentialclockinputs(CK,/CK)operation •Doubledatarateinterface •Sourcesynchronous-d

HynixHynix Semiconductor

SK海力士海力士半导体

Hynix

1Gb(64Mx16) DDR2 SDRAM

Description DeviceFeatures&OrderingInformation KeyFeatures •VDD=1.8+/-0.1V •VDDQ=1.8+/-0.1V •AllinputsandoutputsarecompatiblewithSSTL_18interface •8banks •Fullydifferentialclockinputs(CK,/CK)operation •Doubledatarateinterface •Sou

HynixHynix Semiconductor

SK海力士海力士半导体

Hynix

1Gb DDR2 SDRAM

Description DeviceFeatures&OrderingInformation KeyFeatures •VDD=1.8+/-0.1V •VDDQ=1.8+/-0.1V •AllinputsandoutputsarecompatiblewithSSTL_18interface •8banks •Fullydifferentialclockinputs(CK,/CK)operation •Doubledatarateinterface •Sourcesynchronous-d

HynixHynix Semiconductor

SK海力士海力士半导体

Hynix

1Gb(64Mx16) DDR2 SDRAM

Description DeviceFeatures&OrderingInformation KeyFeatures •VDD=1.8+/-0.1V •VDDQ=1.8+/-0.1V •AllinputsandoutputsarecompatiblewithSSTL_18interface •8banks •Fullydifferentialclockinputs(CK,/CK)operation •Doubledatarateinterface •Sou

HynixHynix Semiconductor

SK海力士海力士半导体

Hynix

1Gb(64Mx16) DDR2 SDRAM

Description DeviceFeatures&OrderingInformation KeyFeatures •VDD=1.8+/-0.1V •VDDQ=1.8+/-0.1V •AllinputsandoutputsarecompatiblewithSSTL_18interface •8banks •Fullydifferentialclockinputs(CK,/CK)operation •Doubledatarateinterface •Sou

HynixHynix Semiconductor

SK海力士海力士半导体

Hynix

1Gb DDR2 SDRAM

Description DeviceFeatures&OrderingInformation KeyFeatures •VDD=1.8+/-0.1V •VDDQ=1.8+/-0.1V •AllinputsandoutputsarecompatiblewithSSTL_18interface •8banks •Fullydifferentialclockinputs(CK,/CK)operation •Doubledatarateinterface •Sou

HynixHynix Semiconductor

SK海力士海力士半导体

Hynix

1Gb DDR2 SDRAM

Description DeviceFeatures&OrderingInformation KeyFeatures •VDD=1.8+/-0.1V •VDDQ=1.8+/-0.1V •AllinputsandoutputsarecompatiblewithSSTL_18interface •8banks •Fullydifferentialclockinputs(CK,/CK)operation •Doubledatarateinterface •Sou

HynixHynix Semiconductor

SK海力士海力士半导体

Hynix

1Gb DDR2 SDRAM

Description DeviceFeatures&OrderingInformation KeyFeatures •VDD=1.8+/-0.1V •VDDQ=1.8+/-0.1V •AllinputsandoutputsarecompatiblewithSSTL_18interface •8banks •Fullydifferentialclockinputs(CK,/CK)operation •Doubledatarateinterface •Sou

HynixHynix Semiconductor

SK海力士海力士半导体

Hynix

1Gb DDR2 SDRAM

Description DeviceFeatures&OrderingInformation KeyFeatures •VDD=1.8+/-0.1V •VDDQ=1.8+/-0.1V •AllinputsandoutputsarecompatiblewithSSTL_18interface •8banks •Fullydifferentialclockinputs(CK,/CK)operation •Doubledatarateinterface •Sou

HynixHynix Semiconductor

SK海力士海力士半导体

Hynix

1Gb DDR2 SDRAM

Description DeviceFeatures&OrderingInformation KeyFeatures •VDD=1.8+/-0.1V •VDDQ=1.8+/-0.1V •AllinputsandoutputsarecompatiblewithSSTL_18interface •8banks •Fullydifferentialclockinputs(CK,/CK)operation •Doubledatarateinterface •Sou

HynixHynix Semiconductor

SK海力士海力士半导体

Hynix

1Gb DDR2 SDRAM

Description DeviceFeatures&OrderingInformation KeyFeatures •VDD=1.8+/-0.1V •VDDQ=1.8+/-0.1V •AllinputsandoutputsarecompatiblewithSSTL_18interface •8banks •Fullydifferentialclockinputs(CK,/CK)operation •Doubledatarateinterface •Sou

HynixHynix Semiconductor

SK海力士海力士半导体

Hynix

1Gb DDR2 SDRAM

KeyFeatures •VDD=1.8+/-0.1V •VDDQ=1.8+/-0.1V •AllinputsandoutputsarecompatiblewithSSTL_18interface •8banks •Fullydifferentialclockinputs(CK,/CK)operation •Doubledatarateinterface •Sourcesynchronous-datatransactionalignedtobidirectionaldatastrobe(DQS

HynixHynix Semiconductor

SK海力士海力士半导体

Hynix

1Gb DDR2 SDRAM

KeyFeatures •VDD=1.8+/-0.1V •VDDQ=1.8+/-0.1V •AllinputsandoutputsarecompatiblewithSSTL_18interface •8banks •Fullydifferentialclockinputs(CK,/CK)operation •Doubledatarateinterface •Sourcesynchronous-datatransactionalignedtobidirectionaldatastrobe(DQS

HynixHynix Semiconductor

SK海力士海力士半导体

Hynix

1Gb DDR2 SDRAM

KeyFeatures •VDD=1.8+/-0.1V •VDDQ=1.8+/-0.1V •AllinputsandoutputsarecompatiblewithSSTL_18interface •8banks •Fullydifferentialclockinputs(CK,/CK)operation •Doubledatarateinterface •Sourcesynchronous-datatransactionalignedtobidirectionaldatastrobe(DQS

HynixHynix Semiconductor

SK海力士海力士半导体

Hynix

1Gb DDR2 SDRAM

KeyFeatures •VDD=1.8+/-0.1V •VDDQ=1.8+/-0.1V •AllinputsandoutputsarecompatiblewithSSTL_18interface •8banks •Fullydifferentialclockinputs(CK,/CK)operation •Doubledatarateinterface •Sourcesynchronous-datatransactionalignedtobidirectionaldatastrobe(DQS

HynixHynix Semiconductor

SK海力士海力士半导体

Hynix

1Gb DDR2 SDRAM

KeyFeatures •VDD=1.8+/-0.1V •VDDQ=1.8+/-0.1V •AllinputsandoutputsarecompatiblewithSSTL_18interface •8banks •Fullydifferentialclockinputs(CK,/CK)operation •Doubledatarateinterface •Sourcesynchronous-datatransactionalignedtobidirectionaldatastrobe(DQS

HynixHynix Semiconductor

SK海力士海力士半导体

Hynix

1Gb DDR2 SDRAM

KeyFeatures •VDD=1.8+/-0.1V •VDDQ=1.8+/-0.1V •AllinputsandoutputsarecompatiblewithSSTL_18interface •8banks •Fullydifferentialclockinputs(CK,/CK)operation •Doubledatarateinterface •Sourcesynchronous-datatransactionalignedtobidirectionaldatastrobe(DQS

HynixHynix Semiconductor

SK海力士海力士半导体

Hynix

1Gb DDR2 SDRAM

KeyFeatures •VDD=1.8+/-0.1V •VDDQ=1.8+/-0.1V •AllinputsandoutputsarecompatiblewithSSTL_18interface •8banks •Fullydifferentialclockinputs(CK,/CK)operation •Doubledatarateinterface •Sourcesynchronous-datatransactionalignedtobidirectionaldatastrobe(DQS

HynixHynix Semiconductor

SK海力士海力士半导体

Hynix

1Gb DDR2 SDRAM

KeyFeatures •VDD=1.8+/-0.1V •VDDQ=1.8+/-0.1V •AllinputsandoutputsarecompatiblewithSSTL_18interface •8banks •Fullydifferentialclockinputs(CK,/CK)operation •Doubledatarateinterface •Sourcesynchronous-datatransactionalignedtobidirectionaldatastrobe(DQS

HynixHynix Semiconductor

SK海力士海力士半导体

Hynix

1Gb DDR2 SDRAM

KeyFeatures •VDD=1.8+/-0.1V •VDDQ=1.8+/-0.1V •AllinputsandoutputsarecompatiblewithSSTL_18interface •8banks •Fullydifferentialclockinputs(CK,/CK)operation •Doubledatarateinterface •Sourcesynchronous-datatransactionalignedtobidirectionaldatastrobe(DQS

HynixHynix Semiconductor

SK海力士海力士半导体

Hynix

1Gb DDR2 SDRAM

KeyFeatures •VDD=1.8+/-0.1V •VDDQ=1.8+/-0.1V •AllinputsandoutputsarecompatiblewithSSTL_18interface •8banks •Fullydifferentialclockinputs(CK,/CK)operation •Doubledatarateinterface •Sourcesynchronous-datatransactionalignedtobidirectionaldatastrobe(DQS

HynixHynix Semiconductor

SK海力士海力士半导体

Hynix

1Gb DDR2 SDRAM

KeyFeatures •VDD=1.8+/-0.1V •VDDQ=1.8+/-0.1V •AllinputsandoutputsarecompatiblewithSSTL_18interface •8banks •Fullydifferentialclockinputs(CK,/CK)operation •Doubledatarateinterface •Sourcesynchronous-datatransactionalignedtobidirectionaldatastrobe(DQS

HynixHynix Semiconductor

SK海力士海力士半导体

Hynix

1Gb DDR2 SDRAM

KeyFeatures •VDD=1.8+/-0.1V •VDDQ=1.8+/-0.1V •AllinputsandoutputsarecompatiblewithSSTL_18interface •8banks •Fullydifferentialclockinputs(CK,/CK)operation •Doubledatarateinterface •Sourcesynchronous-datatransactionalignedtobidirectionaldatastrobe(DQS

HynixHynix Semiconductor

SK海力士海力士半导体

Hynix

1Gb DDR2 SDRAM

KeyFeatures •VDD=1.8+/-0.1V •VDDQ=1.8+/-0.1V •AllinputsandoutputsarecompatiblewithSSTL_18interface •8banks •Fullydifferentialclockinputs(CK,/CK)operation •Doubledatarateinterface •Sourcesynchronous-datatransactionalignedtobidirectionaldatastrobe(DQS

HynixHynix Semiconductor

SK海力士海力士半导体

Hynix

1Gb DDR2 SDRAM

KeyFeatures •VDD=1.8+/-0.1V •VDDQ=1.8+/-0.1V •AllinputsandoutputsarecompatiblewithSSTL_18interface •8banks •Fullydifferentialclockinputs(CK,/CK)operation •Doubledatarateinterface •Sourcesynchronous-datatransactionalignedtobidirectionaldatastrobe(DQS

HynixHynix Semiconductor

SK海力士海力士半导体

Hynix

1Gb DDR2 SDRAM

KeyFeatures •VDD=1.8+/-0.1V •VDDQ=1.8+/-0.1V •AllinputsandoutputsarecompatiblewithSSTL_18interface •8banks •Fullydifferentialclockinputs(CK,/CK)operation •Doubledatarateinterface •Sourcesynchronous-datatransactionalignedtobidirectionaldatastrobe(DQS

HynixHynix Semiconductor

SK海力士海力士半导体

Hynix

1Gb DDR2 SDRAM

KeyFeatures •VDD=1.8+/-0.1V •VDDQ=1.8+/-0.1V •AllinputsandoutputsarecompatiblewithSSTL_18interface •8banks •Fullydifferentialclockinputs(CK,/CK)operation •Doubledatarateinterface •Sourcesynchronous-datatransactionalignedtobidirectionaldatastrobe(DQS

HynixHynix Semiconductor

SK海力士海力士半导体

Hynix

1Gb DDR2 SDRAM

KeyFeatures •VDD=1.8+/-0.1V •VDDQ=1.8+/-0.1V •AllinputsandoutputsarecompatiblewithSSTL_18interface •8banks •Fullydifferentialclockinputs(CK,/CK)operation •Doubledatarateinterface •Sourcesynchronous-datatransactionalignedtobidirectionaldatastrobe(DQS

HynixHynix Semiconductor

SK海力士海力士半导体

Hynix

1Gb DDR2 SDRAM

KeyFeatures •VDD=1.8+/-0.1V •VDDQ=1.8+/-0.1V •AllinputsandoutputsarecompatiblewithSSTL_18interface •8banks •Fullydifferentialclockinputs(CK,/CK)operation •Doubledatarateinterface •Sourcesynchronous-datatransactionalignedtobidirectionaldatastrobe(DQS

HynixHynix Semiconductor

SK海力士海力士半导体

Hynix

1Gb DDR2 SDRAM

KeyFeatures •VDD=1.8+/-0.1V •VDDQ=1.8+/-0.1V •AllinputsandoutputsarecompatiblewithSSTL_18interface •8banks •Fullydifferentialclockinputs(CK,/CK)operation •Doubledatarateinterface •Sourcesynchronous-datatransactionalignedtobidirectionaldatastrobe(DQS

HynixHynix Semiconductor

SK海力士海力士半导体

Hynix

1Gb DDR2 SDRAM

KeyFeatures •VDD=1.8+/-0.1V •VDDQ=1.8+/-0.1V •AllinputsandoutputsarecompatiblewithSSTL_18interface •8banks •Fullydifferentialclockinputs(CK,/CK)operation •Doubledatarateinterface •Sourcesynchronous-datatransactionalignedtobidirectionaldatastrobe(DQS

HynixHynix Semiconductor

SK海力士海力士半导体

Hynix

1Gb DDR2 SDRAM

KeyFeatures •VDD=1.8+/-0.1V •VDDQ=1.8+/-0.1V •AllinputsandoutputsarecompatiblewithSSTL_18interface •8banks •Fullydifferentialclockinputs(CK,/CK)operation •Doubledatarateinterface •Sourcesynchronous-datatransactionalignedtobidirectionaldatastrobe(DQS

HynixHynix Semiconductor

SK海力士海力士半导体

Hynix

1Gb DDR2 SDRAM

KeyFeatures •VDD=1.8+/-0.1V •VDDQ=1.8+/-0.1V •AllinputsandoutputsarecompatiblewithSSTL_18interface •8banks •Fullydifferentialclockinputs(CK,/CK)operation •Doubledatarateinterface •Sourcesynchronous-datatransactionalignedtobidirectionaldatastrobe(DQS

HynixHynix Semiconductor

SK海力士海力士半导体

Hynix

1Gb DDR2 SDRAM

KeyFeatures •VDD=1.8+/-0.1V •VDDQ=1.8+/-0.1V •AllinputsandoutputsarecompatiblewithSSTL_18interface •8banks •Fullydifferentialclockinputs(CK,/CK)operation •Doubledatarateinterface •Sourcesynchronous-datatransactionalignedtobidirectionaldatastrobe(DQS

HynixHynix Semiconductor

SK海力士海力士半导体

Hynix

1Gb DDR2 SDRAM

KeyFeatures •VDD=1.8+/-0.1V •VDDQ=1.8+/-0.1V •AllinputsandoutputsarecompatiblewithSSTL_18interface •8banks •Fullydifferentialclockinputs(CK,/CK)operation •Doubledatarateinterface •Sourcesynchronous-datatransactionalignedtobidirectionaldatastrobe(DQS

HynixHynix Semiconductor

SK海力士海力士半导体

Hynix

1Gb DDR2 SDRAM

KeyFeatures •VDD=1.8+/-0.1V •VDDQ=1.8+/-0.1V •AllinputsandoutputsarecompatiblewithSSTL_18interface •8banks •Fullydifferentialclockinputs(CK,/CK)operation •Doubledatarateinterface •Sourcesynchronous-datatransactionalignedtobidirectionaldatastrobe(DQS

HynixHynix Semiconductor

SK海力士海力士半导体

Hynix

1Gb DDR2 SDRAM

Description DeviceFeatures&OrderingInformation KeyFeatures •VDD=1.8+/-0.1V •VDDQ=1.8+/-0.1V •AllinputsandoutputsarecompatiblewithSSTL_18interface •8banks •Fullydifferentialclockinputs(CK,/CK)operation •Doubledatarateinterface •Sourcesynchronous-d

HynixHynix Semiconductor

SK海力士海力士半导体

Hynix

1Gb DDR2 SDRAM

DeviceFeatures&OrderingInformation KeyFeatures •VDD=1.8+/-0.1V •VDDQ=1.8+/-0.1V •AllinputsandoutputsarecompatiblewithSSTL_18interface •8banks •Fullydifferentialclockinputs(CK,/CK)operation •Doubledatarateinterface •Sourcesynchronous-datatransacti

HynixHynix Semiconductor

SK海力士海力士半导体

Hynix

1Gb DDR2 SDRAM

DeviceFeatures&OrderingInformation KeyFeatures •VDD=1.8+/-0.1V •VDDQ=1.8+/-0.1V •AllinputsandoutputsarecompatiblewithSSTL_18interface •8banks •Fullydifferentialclockinputs(CK,/CK)operation •Doubledatarateinterface •Sourcesynchronous-datatransacti

HynixHynix Semiconductor

SK海力士海力士半导体

Hynix

1Gb DDR2 SDRAM

DeviceFeatures&OrderingInformation KeyFeatures •VDD=1.8+/-0.1V •VDDQ=1.8+/-0.1V •AllinputsandoutputsarecompatiblewithSSTL_18interface •8banks •Fullydifferentialclockinputs(CK,/CK)operation •Doubledatarateinterface •Sourcesynchronous-datatransacti

HynixHynix Semiconductor

SK海力士海力士半导体

Hynix

1Gb DDR2 SDRAM

DeviceFeatures&OrderingInformation KeyFeatures •VDD=1.8+/-0.1V •VDDQ=1.8+/-0.1V •AllinputsandoutputsarecompatiblewithSSTL_18interface •8banks •Fullydifferentialclockinputs(CK,/CK)operation •Doubledatarateinterface •Sourcesynchronous-datatransacti

HynixHynix Semiconductor

SK海力士海力士半导体

Hynix

1Gb DDR2 SDRAM

DeviceFeatures&OrderingInformation KeyFeatures •VDD=1.8+/-0.1V •VDDQ=1.8+/-0.1V •AllinputsandoutputsarecompatiblewithSSTL_18interface •8banks •Fullydifferentialclockinputs(CK,/CK)operation •Doubledatarateinterface •Sourcesynchronous-datatransacti

HynixHynix Semiconductor

SK海力士海力士半导体

Hynix

1Gb DDR2 SDRAM

DeviceFeatures&OrderingInformation KeyFeatures •VDD=1.8+/-0.1V •VDDQ=1.8+/-0.1V •AllinputsandoutputsarecompatiblewithSSTL_18interface •8banks •Fullydifferentialclockinputs(CK,/CK)operation •Doubledatarateinterface •Sourcesynchronous-datatransacti

HynixHynix Semiconductor

SK海力士海力士半导体

Hynix

256Mb DDR2 SDRAM

KeyFeatures •VDD,VDDQ=1.8+/-0.1V •AllinputsandoutputsarecompatiblewithSSTL_18interface •Fullydifferentialclockinputs(CK,/CK)operation •Doubledatarateinterface •Sourcesynchronous-datatransactionalignedtobidirectionaldatastrobe(DQS,DQS) •DifferentialDataS

HynixHynix Semiconductor

SK海力士海力士半导体

Hynix

256Mb DDR2 SDRAM

KeyFeatures •VDD,VDDQ=1.8+/-0.1V •AllinputsandoutputsarecompatiblewithSSTL_18interface •Fullydifferentialclockinputs(CK,/CK)operation •Doubledatarateinterface •Sourcesynchronous-datatransactionalignedtobidirectionaldatastrobe(DQS,DQS) •DifferentialDataS

HynixHynix Semiconductor

SK海力士海力士半导体

Hynix

256Mb DDR2 SDRAM

KeyFeatures •VDD,VDDQ=1.8+/-0.1V •AllinputsandoutputsarecompatiblewithSSTL_18interface •Fullydifferentialclockinputs(CK,/CK)operation •Doubledatarateinterface •Sourcesynchronous-datatransactionalignedtobidirectionaldatastrobe(DQS,DQS) •DifferentialDataS

HynixHynix Semiconductor

SK海力士海力士半导体

Hynix

256Mb DDR2 SDRAM

KeyFeatures •VDD,VDDQ=1.8+/-0.1V •AllinputsandoutputsarecompatiblewithSSTL_18interface •Fullydifferentialclockinputs(CK,/CK)operation •Doubledatarateinterface •Sourcesynchronous-datatransactionalignedtobidirectionaldatastrobe(DQS,DQS) •DifferentialDataS

HynixHynix Semiconductor

SK海力士海力士半导体

Hynix

256Mb DDR2 SDRAM

KeyFeatures •VDD,VDDQ=1.8+/-0.1V •AllinputsandoutputsarecompatiblewithSSTL_18interface •Fullydifferentialclockinputs(CK,/CK)operation •Doubledatarateinterface •Sourcesynchronous-datatransactionalignedtobidirectionaldatastrobe(DQS,DQS) •DifferentialDataS

HynixHynix Semiconductor

SK海力士海力士半导体

Hynix

256Mb DDR2 SDRAM

KeyFeatures •VDD,VDDQ=1.8+/-0.1V •AllinputsandoutputsarecompatiblewithSSTL_18interface •Fullydifferentialclockinputs(CK,/CK)operation •Doubledatarateinterface •Sourcesynchronous-datatransactionalignedtobidirectionaldatastrobe(DQS,DQS) •DifferentialDataS

HynixHynix Semiconductor

SK海力士海力士半导体

Hynix

256Mb DDR2 SDRAM

KeyFeatures •VDD,VDDQ=1.8+/-0.1V •AllinputsandoutputsarecompatiblewithSSTL_18interface •Fullydifferentialclockinputs(CK,/CK)operation •Doubledatarateinterface •Sourcesynchronous-datatransactionalignedtobidirectionaldatastrobe(DQS,DQS) •DifferentialDataS

HynixHynix Semiconductor

SK海力士海力士半导体

Hynix

256Mb DDR2 SDRAM

KeyFeatures •VDD,VDDQ=1.8+/-0.1V •AllinputsandoutputsarecompatiblewithSSTL_18interface •Fullydifferentialclockinputs(CK,/CK)operation •Doubledatarateinterface •Sourcesynchronous-datatransactionalignedtobidirectionaldatastrobe(DQS,DQS) •DifferentialDataS

HynixHynix Semiconductor

SK海力士海力士半导体

Hynix

256Mb DDR2 SDRAM

KeyFeatures •VDD,VDDQ=1.8+/-0.1V •AllinputsandoutputsarecompatiblewithSSTL_18interface •Fullydifferentialclockinputs(CK,/CK)operation •Doubledatarateinterface •Sourcesynchronous-datatransactionalignedtobidirectionaldatastrobe(DQS,DQS) •DifferentialDataS

HynixHynix Semiconductor

SK海力士海力士半导体

Hynix

256Mb DDR2 SDRAM

KeyFeatures •VDD,VDDQ=1.8+/-0.1V •AllinputsandoutputsarecompatiblewithSSTL_18interface •Fullydifferentialclockinputs(CK,/CK)operation •Doubledatarateinterface •Sourcesynchronous-datatransactionalignedtobidirectionaldatastrobe(DQS,DQS) •DifferentialDataS

HynixHynix Semiconductor

SK海力士海力士半导体

Hynix

256Mb DDR2 SDRAM

KeyFeatures •VDD,VDDQ=1.8+/-0.1V •AllinputsandoutputsarecompatiblewithSSTL_18interface •Fullydifferentialclockinputs(CK,/CK)operation •Doubledatarateinterface •Sourcesynchronous-datatransactionalignedtobidirectionaldatastrobe(DQS,DQS) •DifferentialDataS

HynixHynix Semiconductor

SK海力士海力士半导体

Hynix

256Mb DDR2 SDRAM

KeyFeatures •VDD,VDDQ=1.8+/-0.1V •AllinputsandoutputsarecompatiblewithSSTL_18interface •Fullydifferentialclockinputs(CK,/CK)operation •Doubledatarateinterface •Sourcesynchronous-datatransactionalignedtobidirectionaldatastrobe(DQS,DQS) •DifferentialDataS

HynixHynix Semiconductor

SK海力士海力士半导体

Hynix

256Mb DDR2 SDRAM

KeyFeatures •VDD,VDDQ=1.8+/-0.1V •AllinputsandoutputsarecompatiblewithSSTL_18interface •Fullydifferentialclockinputs(CK,/CK)operation •Doubledatarateinterface •Sourcesynchronous-datatransactionalignedtobidirectionaldatastrobe(DQS,DQS) •DifferentialDataS

HynixHynix Semiconductor

SK海力士海力士半导体

Hynix

256Mb DDR2 SDRAM

KeyFeatures •VDD,VDDQ=1.8+/-0.1V •AllinputsandoutputsarecompatiblewithSSTL_18interface •Fullydifferentialclockinputs(CK,/CK)operation •Doubledatarateinterface •Sourcesynchronous-datatransactionalignedtobidirectionaldatastrobe(DQS,DQS) •DifferentialDataS

HynixHynix Semiconductor

SK海力士海力士半导体

Hynix

256Mb DDR2 SDRAM

KeyFeatures •VDD,VDDQ=1.8+/-0.1V •AllinputsandoutputsarecompatiblewithSSTL_18interface •Fullydifferentialclockinputs(CK,/CK)operation •Doubledatarateinterface •Sourcesynchronous-datatransactionalignedtobidirectionaldatastrobe(DQS,DQS) •DifferentialDataS

HynixHynix Semiconductor

SK海力士海力士半导体

Hynix

256Mb DDR2 SDRAM

KeyFeatures •VDD,VDDQ=1.8+/-0.1V •AllinputsandoutputsarecompatiblewithSSTL_18interface •Fullydifferentialclockinputs(CK,/CK)operation •Doubledatarateinterface •Sourcesynchronous-datatransactionalignedtobidirectionaldatastrobe(DQS,DQS) •DifferentialDataS

HynixHynix Semiconductor

SK海力士海力士半导体

Hynix

H5P产品属性

  • 类型

    描述

  • 型号

    H5P

  • 制造商

    BOTHHAND

  • 制造商全称

    Bothhand USA, LP.

  • 功能描述

    10/100 BASE-T FIVE PORT MAGNETICS

更新时间:2024-6-6 11:54:00
IC供应商 芯片型号 品牌 批号 封装 库存 备注 价格
H5PNM
2
2
SKHYNIX
存储器
FBGA
40018
HYNIX原装存储芯片-诚信为本
HYNIX
2016+
FBGA
6523
只做进口原装现货!假一赔十!
HYNIX
23+
BGA
15000
全新原装现货,价格优势
JST
2308+
122867
一级代理,原装正品,公司现货!
LB
2018+
DIP
6000
全新原装正品现货,假一赔佰
HYNIX
22+
BGA
25460
中国著名的电子元器件独立分销商 ,原厂核心渠道! 专业致力于:Memory、FPGA、光耦、二三极管、单片机、处理器、MOS管..
HYNIX
2014+
BGA/TSOP
20000
SAMSUNG,NANYA亚太地区一级代理商,全新原装进口现
HYNIX
2024+原装现货
BGA
8950
BOM配单专家,发货快,价格低
SAMSUNG/三星
21+
BGA
9080
只做原装,质量保证

H5P芯片相关品牌

  • ANALOGICTECH
  • ASTRODYNE
  • CT
  • DSK
  • EIC
  • EMCORE
  • MTRONPTI
  • NTE
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  • SLPOWER
  • TALEMA
  • Yamaha

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