Low Skew, Low Additive Jitter 3 x 5 LVPECL/LVDS/HCSL Fanout Buffer with one LVCMOS output

Features • 3 to 1 input Multiplexer: Two inputs accept any differential (LVPECL, HCSL, LVDS, SSTL, CML, LVCMOS) or a single ended signal and the third input accepts a crystal or a single ended signal • Five differential LVPECL/LVDS/HCSL outputs and one LVCMOS output • Ultra-low additive jitter:

Low Skew, Low Additive Jitter 3 x 5 LVPECL/LVDS/HCSL Fanout Buffer with one LVCMOS output

Features • 3 to 1 input Multiplexer: Two inputs accept any differential (LVPECL, HCSL, LVDS, SSTL, CML, LVCMOS) or a single ended signal and the third input accepts a crystal or a single ended signal • Five differential LVPECL/LVDS/HCSL outputs and one LVCMOS output • Ultra-low additive jitter:

Low Skew, Low Additive Jitter 3 x 5 LVPECL/LVDS/HCSL Fanout Buffer with one LVCMOS output

Features • 3 to 1 input Multiplexer: Two inputs accept any differential (LVPECL, HCSL, LVDS, SSTL, CML, LVCMOS) or a single ended signal and the third input accepts a crystal or a single ended signal • Five differential LVPECL/LVDS/HCSL outputs and one LVCMOS output • Ultra-low additive jitter:

封装/外壳：40-VFQFN 裸露焊盘 包装：卷带（TR） 描述：LOW SKEW, LOW ADDITIVE JITTER 2 集成电路（IC） 时钟缓冲器，驱动器

封装/外壳：40-VFQFN 裸露焊盘 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：LOW SKEW, LOW ADDITIVE JITTER 2 集成电路（IC） 时钟缓冲器，驱动器

Integrated System Management IC Triple Voltage Monitors, POR, 2 kbit EEPROM Memory, and Single/Dual DCP

FEATURES • Triple Voltage Monitors —User Programmable Threshold Voltage —Power-on Reset (POR) Circuitry —Software Selectable Reset timeout —Manual Reset Input • 2-Wire industry standard Serial Interface • 2 kbit EEPROM with Write Protect & Block LockTM • Digitally Controlled Potentiometers

GERMANIUM PNP TRANSISTORS

文件：2.44311 Mbytes Page：6 Pages

SI-40235

文件：342.86 Kbytes Page：4 Pages

Triple Voltage Monitors, POR, 2 kbit EEPROM MEMORY, and Single/Dual DCP

文件：541.57 Kbytes Page：36 Pages