FEATURES

 Single power supply operation

- Full voltage range: 2.7-3.6 volt

 Serial Interface Architecture

- SPI Compatible: Mode 0 and Mode 3

 128 M-bit Serial Flash

- 128 M-bit / 16,384 KByte /65,535 pages

- 256 bytes per programmable page

 Standard, Dual or Quad SPI

- Standard SPI: CLK, CS#, DI, DO, WP#,

HOLD#/RESET#

- Dual SPI: CLK, CS#, DQ0, DQ1, WP#,

HOLD#/RESET#

- Quad SPI: CLK, CS#, DQ0, DQ1, DQ2, DQ3

- Configurable dummy cycle number

 High performance

- Normal read

- 50MHz

- Fast read (Single Data Rate Mode)

- Standard SPI: 104MHz with 1 dummy bytes

- Dual SPI: 104MHz with 1 dummy bytes

- Quad SPI: 104MHz with 3 dummy bytes

 Write Suspend and Write Resume

 Support Serial Flash Discoverable

Parameters (SFDP) signature

 Low power consumption

- 5 mA typical active current

- 1A typical power down current

 Uniform Sector Architecture:

- 4096 sectors of 4-Kbyte

- 512 blocks of 32-Kbyte

- 256 blocks of 64-Kbyte

- Any sector or block can be erased individually

 Software and Hardware Write Protection:

- Write Protect all or portion of memory via

software

- Enable/Disable protection with WP# pin

 Software and Hardware Reset

 High performance program/erase speed

- Page program time: 0.5ms typical

- Sector erase time: 40ms typical

- Half Block erase time 200ms typical

- Block erase time 300ms typical

- Chip erase time: 60 Seconds typical

 Volatile Status Register Bits.

 Lockable 512 byte OTP security sector

 Read Unique ID Number

 Typical 100K endurance cycle

 Data retention time 20years

 Package Options

- SOP 208mil 8L

- WSON 5x6 8L

- TFBGA 6x8 24ball

- All Pb-free packages are compliant RoHS,

Halogen-Free and REACH.

 Industrial temperature Range

GENERAL DESCRIPTION

The XM25QH128A is a 128 Megabit (16,384K-byte) Serial Flash memory, with advanced write

protection mechanisms. The XM25QH128A supports the single bit and four bits serial input and output

commands via standard Serial Peripheral Interface (SPI) pins: Serial Clock, Chip Select, Serial DQ0 (DI)

and DQ1(DO), DQ2(WP#) and DQ3(HOLD#/RESET#). SPI clock frequencies of up to 104Mhz are

supported allowing equivalent clock rates of 416Mhz(104Mhz x 4) for Quad Output while using the Quad

Output read instructions. The memory can be programmed 1 to 256 bytes at a time, using the Page

Program instruction.

The XM25QH128A also offers a sophisticated method for protecting individual blocks against erroneous

or malicious program and erase operations. By providing the ability to individually protect and unprotect

blocks, a system can unprotect a specific block to modify its contents while keeping the remaining

blocks of the memory array securely protected. This is useful in applications where program code is

patched or updated on a subroutine or module basis or in applications where data storage segments

need to be modified without running the risk of errant modifications to the program code segments.

The XM25QH128A is designed to allow either single Sector/Block at a time or full chip erase operation.

The XM25QH128A can be configured to protect part of the memory as the software protected mode.

The device can sustain a typical of 100K program/erase cycles on each sector or block.