FEATURES

■ Access Times of 35ns (SRAM) and 90ns (FLASH)

■ Packaging

• 66 pin, PGA Type, 1.075 square HIP, Hermetic Ceramic HIP (Package 400)

• 68 lead, Hermetic CQFP (G2U), 22.4mm (0.880) square (Package 510) 3.56mm (0.140) height. Designed to fi t JEDEC 68 lead 0.990” CQFJ footprint (FIGURE 2)

■ 128Kx16 SRAM

■ 512Kx16 5V FLASH

■ Organized as 128Kx16 of SRAM and 512Kx16 of Flash Memory with separate Data Buses

■ Both blocks of memory are User Confi gurable as 256Kx8

■ Low Power CMOS

■ Commercial, Industrial and Military Temperature Ranges

■ TTL Compatible Inputs and Outputs

■ Built-in Decoupling Caps and Multiple Ground Pins for Low Noise Operation

■ Weight:

WSF2816-39G2UX - 8 grams typical

WSF2816-39H1X - 13 grams typical

FLASH MEMORY FEATURES

■ 100,000 Erase/Program Cycles

■ Sector Architecture

• 8 equal size sectors of 64K bytes each

• Any combination of sectors can be concurrently erased. Also supports full chip erase

■ 5 Volt Programming; 5V ± 10 Supply

■ Embedded Erase and Program Algorithms

■ Hardware Write Protection