FEATURES

■ Access Times of 25ns (SRAM) and 70, 90 and 120ns (FLASH)

■ Packaging:

• 66-pin, PGA Type, 1.385 inch square HIP, Hermetic Ceramic HIP (Package 402)

■ 128Kx32 SRAM

■ 128Kx32 5V Flash

■ Organized as 128Kx32 of SRAM and 128Kx32 of Flash Memory with common Data Bus

■ Low Power CMOS

■ Commercial, Industrial and Military Temperature Ranges

■ TTL Compatible Inputs and Outputs

■ Built-in Decoupling Caps and Multiple Ground Pins for Low Noise Operation

■ Weight - 13 grams typical

FLASH MEMORY FEATURES

■ 10,000 Erase/Program Cycles

■ Sector Architecture

• 8 equal size sectors of 16K bytes each

• Any combination of sectors can be concurrently erased. Also supports full chip erase

■ 5 Volt Programming; 5V ± 10 Supply

■ Embedded Erase and Program Algorithms

■ Hardware Write Protection

■ Page Program Operation and Internal Program Control Time.