FEATURES

■ Access Times of 35ns (SRAM) and 150ns (EEPROM)

■ Access Times of 45ns (SRAM) and 120ns (EEPROM)

■ Access Times of 70ns (SRAM) and 300ns (EEPROM)

■ Packaging

• 66 pin, PGA Type, 1.075 square HIP, Hermetic Ceramic HIP (H1) (Package 400)

• 68 lead, Hermetic CQFP (G2T), 22mm (0.880) square (Package 509). Designed to fi t JEDEC 68 lead 0.990 CQFJ footprint (FIGURE 2)

■ 128Kx16 SRAM

■ 128Kx16 EEPROM

■ Organized as 128Kx16 of SRAM and 128Kx16 of EEPROM Memory with separate Data Buses

■ Both blocks of memory are User Confi gurable as 256Kx8

■ Low Power CMOS

■ Commercial, Industrial and Military Temperature Ranges

■ TTL Compatible Inputs and Outputs

■ Built-in Decoupling Caps and Multiple Ground Pins for Low Noise Operation

■ Weight - 13 grams typical

EEPROM MEMORY FEATURES

■ Write Endurance 10,000 Cycles

■ Data Retention at 25°C, 10 Years

■ Low Power CMOS Operation

■ Automatic Page Write Operation

■ Page Write Cycle Time 10ms Max.

■ Data Polling for End of Write Detection

■ Hardware and Software Data Protection

■ TTL Compatible Inputs and Outputs