FEATURES

■ Organized as 2Mx32

■ Commercial, Industrial, and Military Temperature Ranges

■ 5 Volt Read and Write. 5V ± 10 Supply.

■ Low Power CMOS

■ Data# Polling and Toggle Bit feature for detection of program or erase cycle completion.

■ Supports reading or programming data to a sector not being erased.

■ RESET# pin resets internal state machine to the read mode.

■ Built in Decoupling Caps and Multiple Ground Pins for Low Noise Operation, Separate Power and Ground Planes to improve noise immunity

■ Access Time of 90, 120, 150ns

■ Packaging:

• 66 pin, PGA Type, 1.185 square, Hermetic Ceramic HIP (Package 401).

• 68 lead, Hermetic CQFP (G2U), 22.4mm (0.880) square (Package 510) 3.56mm (0.140) height. Designed to fi t JEDEC 68 lead 0.990 CQFJ footprint (FIGURE 3)

■ Sector Architecture

• 32 equal size sectors of 64KBytes per each 2Mx8 chip

• Any combination of sectors can be erased. Also supports full chip erase.

■ Minimum 100,000 Write/Erase Cycles Minimum