GENERAL DESCRIPTION

The VSC9180 is a multi-rate SONET/SDH transceiver with support for working and protection hitless backplane 1+1 protection. It is designed to serialize four STS-12/STM-4 signals, or byte interleaved SONET/SDH data from 4-bit 622MHz or 16-bit 155MHz parallel buses onto redundant 2.5Gb/s serial backplane outputs.

FEATURES :

Parallel to Serial Transmit

► Receives 16 or 4-Bit Parallel LVDS/LVPECL Inputs Operating

at 155MHz or 622MHz into Internal FIFO using Source

Synchronous Timing

► 16-Bit 155MHz Bus or 4-Bit 622MHz Bus is Bit Multiplexed

to Serial 2.5GHz Output

► Retimes Four Serial STS-12/STM-4 Inputs and Deskews up

to +/- 3 Bytes of Skew using the A1/A2 Boundaries

► Byte Interleaves Four Serial STS-12/STM-4 Inputs to Create

an STS-48 like Signal

► Clear Channel Non-SONET/SDH Capability and Support for

Both SONET/SDH and G.709 OTU1 Frames

Serial to Parallel Receive

► Dual 2.5Gb/s Frequency Synchronous Serial CML Inputs

with Onboard Clock and Data Recovery

► Onboard Frame Alignment of Received Signals and Large

Internal FIFO for Tolerance of up to +/-75ns of Serial

Backplane Skew

► Realignment of Incoming Signals Allows Hitless Selection of

Incoming Channel for Maintenance Purposes, and Prevents

Downstream Devices from Having to Reframe in a Failure

Condition

VSC9180 Arapahoe - 2.5G SONET/SDH Backplane Transceiver

► Hardware Based Switch Over within Receipt of Two or Four Errored

Frame Boundaries

► Loss of Signal, Loss of Alignment, and Loss of Frame Alarm Indication

► Received Frame Pointer Output

► Programmable BER Threshold Monitors Based on B1 Parity Monitoring

of Both Serial Inputs

► Returns 16 or 4-Bit Parallel LVDS Bit De-multiplexed Outputs Operating

at 155MHz or 622MHz with Recovered Bus Clock (Non Interleave Mode)

► Returns Quad STS-12/STM-4 Outputs Operating at 622 Mb/s (Interleave Mode)

► Clear Channel Non-SONET/SDH Capability and Support for Both

SONET/SDH and G.709 OTU1 Frames

Special Features

► 4-Bit or 16-Bit Parallel Bus Loopback with Output Bus Clock

► Parallel Loopback also Allows Quad STS-12/STM-4 Retime, Realign, and

Loopback Output

► Serial Loopback with Hitless Input Selection and Realignment

► Onboard Discrete CMU and CRU to Accommodate Non-synchronous

TX/RX Applications