2.488GHz SONET/SDH Clock Generator

General Description The VSC8121 is a monolithic Phase Locked Loop (PLL) based clock generator designed for telecommunications systems operating at 2.5Gb/s. The VSC8121 incorporates a reactance-based (LC) Voltage Controlled Oscillator (VCO) with low phase noise. The PLL’s loop filter is on-chip.

5V, 1A Linear Regulator with and ENABLE RESET

Description The CS8121 is a 5V, 1A precision linear regulator with two microprocessor compatible control functions and protection circuitry included on chip. The composite NPN-PNP output pass transistor assures a lower dropout voltage (1.2V @ 1A) without requiring excessive supply current (4mA).

Monolithic, 12-Bit Data Acquisition System

DESCRIPTION The SP8121 is a complete data acquisition systems, featuring 8-channel multiplexer, internal reference and 12-bit sampling A/D converter implemented as a single monolithic IC. The analog multiplexer accepts 0V to +5V unipolar full scale inputs. Output data is formatted in 12-bit paral

Monolithic, 12-Bit Data Acquisition System

DESCRIPTION The SP8121 is a complete data acquisition systems, featuring 8-channel multiplexer, internal reference and 12-bit sampling A/D converter implemented as a single monolithic IC. The analog multiplexer accepts 0V to +5V unipolar full scale inputs. Output data is formatted in 12-bit paral

Monolithic, 12-Bit Data Acquisition System

DESCRIPTION The SP8121 is a complete data acquisition systems, featuring 8-channel multiplexer, internal reference and 12-bit sampling A/D converter implemented as a single monolithic IC. The analog multiplexer accepts 0V to +5V unipolar full scale inputs. Output data is formatted in 12-bit paral

Monolithic, 12-Bit Data Acquisition System

DESCRIPTION The SP8121 is a complete data acquisition systems, featuring 8-channel multiplexer, internal reference and 12-bit sampling A/D converter implemented as a single monolithic IC. The analog multiplexer accepts 0V to +5V unipolar full scale inputs. Output data is formatted in 12-bit paral