N-Channel Enhancement-Mode Vertical DMOS Power FETs?

Advanced DMOS Technology These enhancement-mode (normally-off) transistors utilize a vertical DMOS structure and Supertexs well-proven silicon-gate manufacturing process. This combination produces devices with the power handling capabilities of bipolar transistors and with the high input impedanc

N-Channel Enhancement-Mode Vertical DMOS FETs

MILITARY GRADE, 14 PIN, 10 TAP TTL ACTIVES

[POLARA] MILITARY GRADE, 14 PIN, 10 TAP TTL ACTIVES

AMC0x00D Precision, ±250mV Input, Basic and Reinforced Isolated Amplifiers With Fixed Gain and Differential Output

1 Features • Linear input voltage range: ±250mV • Supply voltage range: – High-side (VDD1): 3.0V to 5.5V – Low-side (VDD2): 3.0V to 5.5V • Fixed gain: 8.2V/V • Differential analog output • Low DC errors: – Offset error: ±0.2mV (maximum) – Offset drift: ±2μV/°C (maximum) – Gain error: ±0.

AMC0x00D-Q1 Automotive, Precision, ±250mV Input, Basic and Reinforced Isolated Amplifiers With Fixed Gain and Differential Output

1 Features • AEC-Q100 qualified for automotive applications: – Temperature grade 1: –40°C to +125°C, TA • Linear input voltage range: ±250mV • Supply voltage range: – High-side (VDD1): 3.0V to 5.5V – Low-side (VDD2): 3.0V to 5.5V • Fixed gain: 8.2V/V • Differential analog output • Low DC

AMC0x00D Precision, ±250mV Input, Basic and Reinforced Isolated Amplifiers With Fixed Gain and Differential Output

1 Features • Linear input voltage range: ±250mV • Supply voltage range: – High-side (VDD1): 3.0V to 5.5V – Low-side (VDD2): 3.0V to 5.5V • Fixed gain: 8.2V/V • Differential analog output • Low DC errors: – Offset error: ±0.2mV (maximum) – Offset drift: ±2μV/°C (maximum) – Gain error: ±0.

Semi-regulated output for bus stability

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