DUAL NPN PRE-BIASED TRANSISTOR

Features • Epitaxial Planar Die Construction • Surface Mount Package Suited for Automated Assembly • Simplifies Circuit Design and Reduces Board Space • Lead Free/RoHS Compliant (Note 1) • Green Device (Note 2)

丝印代码：G4；NPN 100mA 50V Complex Digital Transistors (Bias Resistor Built-in Transistors)

Features 1) Two DTC114T chips in a EMT or UMT or SMT package. 2) Mounting cost and area can be cut in half. Application INVERTER, INTERFACE, DRIVER

丝印代码：G4；General purpose (dual digital transistors)

Features 1) Two DTC114T chips in a EMT or UMT or SMT package. 2) Mounting cost and area can be cut in half. Application INVERTER, INTERFACE, DRIVER

Dual Digital Transistors

Dual Digital Transistors (NPN+NPN) FEATURES Two DTC114T chips in a package

丝印代码：G4；Dual NPN Digital Transistors

FEATURES • Two DTC114T (NPN) chips in a package.

Complex Transistor(DTR+DTR)

在超小型封装中内藏2个晶体管。适用于从差动增幅回路到高频水晶振动器，起动器等各种用途。 •输入电阻型超小型复合三极管;

DUAL NPN PRE-BIASED TRANSISTOR

Features • Epitaxial Planar Die Construction • Surface Mount Package Suited for Automated Assembly • Simplifies Circuit Design and Reduces Board Space • Lead Free/RoHS Compliant (Note 1) • Green Device (Note 2)

NPN 100mA 50V Complex Digital Transistors

Features 1) Two DTC114T chips in a EMT or UMT or SMT package. 2) Mounting cost and area can be cut in half. Application INVERTER, INTERFACE, DRIVER

丝印代码：G4；General purpose (dual digital transistors)

文件：84.61 Kbytes Page：3 Pages

丝印代码：G4；General purpose (dual digital transistors)

文件：48.76 Kbytes Page：3 Pages

丝印代码：G4；Emitter common(dual digital transistor)

文件：1.33347 Mbytes Page：10 Pages

Digital Transistor

双数字晶体管