Members of the Texas Instruments

WidebusE Family

State-of-the-Art EPIC-IIBE BiCMOS Design

Significantly Reduces Power Dissipation

ESD Protection Exceeds 2000 V Per

MIL-STD-883, Method 3015; Exceeds 200 V

Using Machine Model (C = 200 pF, R = 0)

Latch-Up Performance Exceeds 500 mA Per

JEDEC Standard JESD-17

Typical VOLP (Output Ground Bounce) < 1 V

at VCC = 5 V, TA = 25°C

High-Impedance State During Power Up

and Power Down

Distributed VCC and GND Pin Configuration

Minimizes High-Speed Switching Noise

Flow-Through Architecture Optimizes PCB

Layout

High-Drive Outputs (–32-mA IOH, 64-mA IOL)

Bus Hold on Data Inputs Eliminates the

Need for External Pullup/Pulldown

Resistors

Package Options Include Plastic 300-mil

Shrink Small-Outline (DL) Package and

380-mil Fine-Pitch Ceramic Flat (WD)

Package Using 25-mil Center-to-Center

Spacings

description

The SN54ABT16260 and SN74ABTH16260 are

12-bit to 24-bit multiplexed D-type latches used in

applications in which two separate data paths

must be multiplexed onto, or demultiplexed from,

a single data path. Typical applications include

multiplexing and/or demultiplexing of address and

data information in microprocessor or

bus-interface applications. This device is also

useful in memory-interleaving applications.

Three 12-bit I/O ports (A1–A12, 1B1–1B12, and 2B1–2B12) are available for address and/or data transfer. The

output-enable (OE1B, OE2B, and OEA) inputs control the bus-transceiver functions. The OE1B and OE2B

control signals also allow bank control in the A-to-B direction.

Address and/or data information can be stored using the internal storage latches. The latch-enable (LE1B,

LE2B, LEA1B, and LEA2B) inputs are used to control data storage. When the latch-enable input is high, the

latch is transparent. When the latch-enable input goes low, the data present at the inputs is latched and remains

latched until the latch-enable input is returned high.