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SN54LS173A中文资料
SN54LS173A数据手册规格书PDF详情
3-State Outputs Interface Directly With
System Bus
Gated Output-Control LInes for Enabling or
Disabling the Outputs
Fully Independent Clock Virtually
Eliminates Restrictions for Operating in
One of Two Modes:
– Parallel Load
– Do Nothing (Hold)
For Application as Bus Buffer Registers
Package Options Include Plastic
Small-Outline (D) Packages, Ceramic Flat
(W) Packages, Ceramic Chip Carriers (FK),
and Standard Plastic (N) and Ceramic (J)
DIPs
description
The ’173 and ’LS173A 4-bit registers include
D-type flip-flops featuring totem-pole 3-state
outputs capable of driving highly capacitive
or relatively low-impedance loads. The
high-impedance third state and increased
high-logic-level drive provide these flip-flops with
the capability of being connected directly to and
driving the bus lines in a bus-organized system without need for interface or pull-up components. Up to 128 of
the SN74173 or SN74LS173A outputs can be connected to a common bus and still drive two Series 54/74 or
54LS/74LS TTL normalized loads, respectively. Similarly, up to 49 of the SN54173 or SN54LS173A outputs can
be connected to a common bus and drive one additional Series 54/74 or 54LS/74LS TTL normalized load,
respectively. To minimize the possibility that two outputs will attempt to take a common bus to opposite logic
levels, the output control circuitry is designed so that the average output disable times are shorter than the
average output enable times.
Gated enable inputs are provided on these devices for controlling the entry of data into the flip-flops. When both
data-enable (G1, G2) inputs are low, data at the D inputs are loaded into their respective flip-flops on the next
positive transition of the buffered clock input. Gate output-control (M, N) inputs also are provided. When both
are low, the normal logic states (high or low levels) of the four outputs are available for driving the loads or bus
lines. The outputs are disabled independently from the level of the clock by a high logic level at either
output-control input. The outputs then present a high impedance and neither load nor drive the bus line. Detailed
operation is given in the function table.
The SN54173 and SN54LS173A are characterized for operation over the full military temperature range of
–55°C to 125°C. The SN74173 and SN74LS173A are characterized for operation from 0°C to 70°C.
SN54LS173A产品属性
- 类型描述 
- 型号SN54LS173A 
- 制造商Texas Instruments 
- 功能描述Flip Flop D-Type Bus Interface Pos-Edge 3-ST 1-Element 16-Pin CDIP Tube 
- 制造商Rochester Electronics LLC 
- 功能描述- Bulk 
- 制造商Texas Instruments 
- 功能描述FLIP FLOP D-TYPE BUS INTRFC POS-EDGE 3-ST 1-ELEM 16CDIP - Rail/Tube 
| 供应商 | 型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 | 
|---|---|---|---|---|---|---|---|
| TI(德州仪器) | 24+ | DIP16 | 907 | 只做原装,提供一站式配单服务,代工代料。BOM配单 | |||
| TI德州仪器 | 22+ | 24000 | 原装正品现货,实单可谈,量大价优 | ||||
| TI | 25+ | SOP16 | 3378 | 绝对原装公司现货供应!价格优势 | |||
| TI | 17+ | DIP | 6200 | 100%原装正品现货 | |||
| TI | DIP | 450 | 正品原装--自家现货-实单可谈 | ||||
| 24+ | DIP16 | 1 | 自己现货 | ||||
| TI | 23+ | QFP | 5000 | 原装正品,假一罚十 | |||
| TI | 25+23+ | DIP | 28416 | 绝对原装正品全新进口深圳现货 | |||
| 最新 | 2000 | 原装正品现货 | |||||
| TI | 23+ | CDIP | 50000 | 全新原装正品现货,支持订货 | 
SN54LS173A 资料下载更多...
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Datasheet数据表PDF页码索引
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