1 Features

1• 6-V to 38-V, Triple Half-Bridge Gate Driver With

Integrated 3x Current Sense Amplifiers (CSA)

– 40-V Absolute Maximum Rating

– Fully Optimized for 12-V and 24-V DC Rails

– Drives High-Side and Low-Side N-Channel

MOSFETs

– Supports 100% PWM Duty Cycle

• Smart Gate-Drive Architecture

– Adjustable Slew-Rate Control for Better EMI

and EMC Performance

– VGS Hand-Shake and Minimum Dead-Time

Insertion to Avoid Shoot-Through

– 15-mA to 150-mA Peak Source Current

– 30-mA to 300-mA Peak Sink Current

• 6x, 3x, 1x and Independent PWM Modes

– Supports 120º Sensored Operation

• Integrated Gate-Driver Power Supplies

– High-Side Doubler Charge Pump

– Low-Side Linear Regulator

• Integrated Triple Current-Shunt Amplifiers

– Adjustable Gain (5, 10, 20, 40 V/V)

– Bidirectional or Unidirectional Support

• SPI or Hardware Device Variants

• Supports 1.8-V, 3.3-V, and 5-V Logic Inputs

• Low-Power Sleep Mode

• Linear Voltage Regulator, 3.3-V, 30-mA

• Integrated Protection Features

– VM Undervoltage Lockout (UVLO)

– Charge Pump Undervoltage (CPUV)

– MOSFET VDS Overcurrent Protection (OCP)

– MOSFET Shoot-Through Protection

– Gate Driver Fault (GDF)

– Thermal Warning and Shutdown (OTW/OTSD)

– Fault Condition Indicator (nFAULT)

2 Applications

• Printers

• BLDC Motor Modules

• White Goods

• CPAPs, Fans, and Pumps

• Drones, Robotics, and RC Toys

• ATM and Currency Counting

3 Description

The DRV8304 device is an integrated gate driver for

3-phase brushless DC (BLDC) motors applications for

12-V and 24-V DC rails. These applications include

field-oriented control (FOC), sinusoidal current

control, and trapezoidal current control of BLDC

motors. The device integrates three current-sense

amplifiers (CSA) for sensing the phase currents of

BLDC motors for optimum FOC and current-control

system implementation. An AUTOCAL feature

automatically calibrates the CSA offset error for

accurate current sensing.

The device is based on smart gate-drive (SGD)

architecture to eliminate the need of any external

gate components (resistors and Zener diodes) while

fully protecting the external FETs. The SGD

architecture optimizes dead time to avoid any shootthrough

conditions, provides flexibility in decreasing

electromagnetic interference (EMI) by gate slew-rate

control, and protects against any gate-short

conditions through VGS hand-shaking and dead time

insertion. Strong pulldown current also prevents any

dv/dt gate turnon.

Various PWM control modes (1x, 3x, 6x, and

independent) are supported for simple interfacing to

control circuits that can be powered by the 30-mA,

3.3-V internal regulator. These modes decrease the

number of output peripherals of the controller for the

specific motor-control requirements and provide

flexibility of control. The device also has a 1x mode

for sensored trapezoidal control of the BLDC motor

by using the internal block-commutation table. The

device can also be configured to drive multiple loads,

such as solenoids, in independent mode.