位置:CDCLVP1204_V01 > CDCLVP1204_V01详情

CDCLVP1204_V01中文资料

厂家型号

CDCLVP1204_V01

文件大小

904.4Kbytes

页面数量

33

功能描述

CDCLVP1204 Four LVPECL Output, High-Performance Clock Buffer

数据手册

下载地址一下载地址二到原厂下载

生产厂商

TI2

CDCLVP1204_V01数据手册规格书PDF详情

1 Features

1• 2:4 Differential Buffer

• Selectable Clock Inputs Through Control Terminal

• Universal Inputs Accept LVPECL, LVDS, and

LVCMOS/LVTTL

• Four LVPECL Outputs

• Maximum Clock Frequency: 2 GHz

• Maximum Core Current Consumption: 45 mA

• Very Low Additive Jitter: <100 fs, RMS in 10-kHz

to 20-MHz Offset Range:

– 57 fs, RMS (typical) at 122.88 MHz

– 48 fs, RMS (typical) at 156.25 MHz

– 30 fs, RMS (typical) at 312.5 MHz

• 2.375-V to 3.6-V Device Power Supply

• Maximum Propagation Delay: 450 ps

• Maximum Output Skew: 15 ps

• LVPECL Reference Voltage, VAC_REF, Available

for Capacitive-Coupled Inputs

• Industrial Temperature Range: –40°C to +85°C

• Supports 105°C PCB Temperature (Measured at

Thermal Pad)

• ESD Protection Exceeds 2 kV (HBM)

2 Applications

• Wireless Communications

• Telecommunications/Networking

• Medical Imaging

• Test and Measurement Equipment

3 Description

The CDCLVP1204 is a highly versatile, low additive

jitter buffer that can generate four copies of LVPECL clock outputs from one of two selectable LVPECL,

LVDS, or LVCMOS inputs for a variety of

communication applications. It has a maximum clock

frequency up to 2 GHz. The CDCLVP1204 features

an on-chip multiplexer (MUX) for selecting one of two inputs that can be easily configured solely through a

control terminal. The overall additive jitter

performance is less than 0.1 ps, RMS from 10 kHz to

20 MHz, and overall output skew is as low as 15 ps,

making the device a perfect choice for use in demanding applications.

The CDCLVP1204 clock buffer distributes one of two selectable clock inputs (IN0, IN1) to four pairs of

differential LVPECL clock outputs (OUT0, OUT3) with

minimum skew for clock distribution. The

CDCLVP1204 can accept two clock sources into an input multiplexer. The inputs can be LVPECL, LVDS,

or LVCMOS/LVTTL.

The CDCLVP1204 is specifically designed for driving 50-Ω transmission lines. When driving the inputs in

single-ended mode, the LVPECL bias voltage

(VAC_REF) must be applied to the unused negative

input terminal. However, for high-speed performance

up to 2 GHz, differential mode is strongly

recommended.

The CDCLVP1204 is characterized for operation from

–40°C to +85°C.

更新时间:2025-11-3 11:06:00
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24+
N/A
47000
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8880
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79
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TI/德州仪器
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79
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22+
5000
TI
23+
QFN
5000
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TI
23+
QFN
3200
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TI/德州仪器
24+
NA/
79
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TI/德州仪器
23+
QFN
6500
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