Low Output Skew for Clock-Distribution

and Clock-Generation Applications

TTL-Compatible Inputs and Outputs

Distributes One Clock Input to Six Clock

Outputs

Polarity Control Selects True or

Complementary Outputs

Distributed VCC and GND Pins Reduce

Switching Noise

High-Drive Outputs (−48-mA IOH,

48-mA IOL)

State-of-the-Art EPIC-ΙΙB BiCMOS Design

Significantly Reduces Power Dissipation

Packaged in Plastic Small-Outline Package

description

The CDC391 contains a clock-driver circuit that distributes one input signal to six outputs with minimum skew

for clock distribution. Through the use of the polarity-control (T/C) inputs, various combinations of true and

complementary outputs can be obtained. The output-enable (OE) input is provided to disable the outputs to a

high-impedance state.

The CDC391 is characterized for operation from −40°C to 85°C.