Low Output Skew for Clock-Distribution

and Clock-Generation Applications

TTL-Compatible Inputs and

CMOS-Compatible Outputs

Distributes One Clock Input to Six Clock

Outputs

Polarity Control Selects True or

Complementary Outputs

Distributed VCC and GND Pins Reduce

Switching Noise

High-Drive Outputs (–32-mA IOH,

32-mA IOL)

State-of-the-Art EPIC-IIBE BiCMOS Design

Significantly Reduces Power Dissipation

Package Options Include Plastic

Small-Outline (D)

description

The CDC329A contains a clock-driver circuit that distributes one input signal to six outputs with minimum skew

for clock distribution. Through the use of the polarity-control inputs (T/C), various combinations of true and

complementary outputs can be obtained.

The CDC329A is characterized for operation from –40°C to 85°C.