Low-Skew Propagation Delay

Specifications for Clock-Driver

Applications

TTL-Compatible Inputs and

CMOS-Compatible Outputs

Flow-Through Architecture Optimizes

PCB Layout

Center-Pin VCC and GND Pin

Configurations Minimize High-Speed

Switching Noise

EPIC  (Enhanced-Performance Implanted

CMOS) 1-μm Process

500-mA Typical Latch-Up Immunity at

125°C

Package Options Include Plastic

Small-Outline (DW)

description

The CDC208 contains dual clock-driver circuits that fanout one input signal to four outputs with minimum skew

for clock distribution (see Figure 2). The device also offers two output-enable (OE1 and OE2) inputs for each

circuit that can force the outputs to be disabled to a high-impedance state or to a high- or low-logic level

independent of the signal on the respective A input.

Skew parameters are specified for a reduced temperature and voltage range common to many applications.

The CDC208 is characterized for operation from −40°C to 85°C.