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CD74AC163中文资料

厂家型号

CD74AC163

文件大小

473.8Kbytes

页面数量

19

功能描述

4-BIT SYNCHRONOUS BINARY COUNTERS

数据手册

原厂下载下载地址一下载地址二到原厂下载

生产厂商

TI2

CD74AC163数据手册规格书PDF详情

Internal Look-Ahead for Fast Counting

Carry Output for n-Bit Cascading

Synchronous Counting

Synchronously Programmable

description/ordering information

The ’AC163 devices are 4-bit binary counters.

These synchronous, presettable counters feature

an internal carry look-ahead for application in

high-speed counting designs. Synchronous

operation is provided by having all flip-flops

clocked simultaneously so that the outputs

change, coincident with each other, when instructed by the count-enable (ENP, ENT) inputs and internal gating.

This mode of operation eliminates the output counting spikes normally associated with synchronous

(ripple-clock) counters. A buffered clock (CLK) input triggers the four flip-flops on the rising (positive-going) edge

of the clock waveform.

The counters are fully programmable; that is, they can be preset to any number between 0 and 9 or 15.

Presetting is synchronous; therefore, setting up a low level at the load input disables the counter and causes

the outputs to agree with the setup data after the next clock pulse, regardless of the levels of the enable inputs.

The clear function is synchronous. A low level at the clear (CLR) input sets all four of the flip-flop outputs low

after the next low-to-high transition of CLK, regardless of the levels of the enable inputs. This synchronous clear

allows the count length to be modified easily by decoding the Q outputs for the maximum count desired. The

active-low output of the gate used for decoding is connected to CLR to synchronously clear the counter to 0000

(LLLL).

The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without

additional gating. ENP, ENT, and a ripple-carry output (RCO) are instrumental in accomplishing this function.

Both ENP and ENT must be high to count, and ENT is fed forward to enable RCO. Enabling RCO produces a

high-level pulse while the count is maximum (9 or 15, with QA high). This high-level overflow ripple-carry pulse

can be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed, regardless of the

level of CLK.

These devices feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD) that

modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of

the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the

stable setup and hold times.

更新时间:2025-10-4 15:09:00
供应商 型号 品牌 批号 封装 库存 备注 价格
TI
23+
16-SOIC
15000
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TI(德州仪器)
24+
SOP16
2669
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TI
24+
PDIP|16
684100
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HARRIS
23+
SOP3.9
5000
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TI德州仪器
22+
24000
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TI
24+
SOIC16
237
TI
25+
SOIC16
4500
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TI
16+
SOIC
10000
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TI
23+
16-DIP
65600
TI
20+
DIP
65790
原装优势主营型号-可开原型号增税票

CD74AC163M96 价格

参考价格:¥1.5426

型号:CD74AC163M96 品牌:TI 备注:这里有CD74AC163多少钱,2025年最近7天走势,今日出价,今日竞价,CD74AC163批发/采购报价,CD74AC163行情走势销售排排榜,CD74AC163报价。