Features

• Fully Static Operation

• Buffered Inputs

• Common Reset

• Positive Edge Clocking

• Typical fMAX = 50MHz at VCC = 5V, CL = 15pF, TA = 25oC

• Fanout (Over Temperature Range)

- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55oC to 125oC

• Balanced Propagation Delay and Transition Times

• Significant Power Reduction Compared to LSTTL

Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: NIL = 30%, NIH = 30% of VCC

at VCC = 5V

Description

The ’HC4017 is a high speed silicon gate CMOS 5-stage

Johnson counter with 10 decoded outputs. Each of the

decoded outputs is normally low and sequentially goes high

on the low to high transition clock period of the 10 clock

period cycle. The CARRY (TC) output transitions low to high

after OUTPUT 10 goes from high to low, and can be used in

conjunction with the CLOCK ENABLE (CE) to cascade

several stages. The CLOCK ENABLE input disables

counting when in the high state. A RESET (MR) input is also

provided which when taken high sets all the decoded

outputs, except “0”, low.

The device can drive up to 10 low power Schottky equivalent

loads.