1 Features

• Latching logic with known power-up state provides

consistent start-up behavior

• Wide operating range of 1.65V to 5.5V

• 5.5V tolerant input pins

• Single-supply voltage translator (refer to LVxT

Enhanced Input Voltage):

– Up translation:

• 1.2V to 1.8V

• 1.5V to 2.5V

• 1.8V to 3.3V

• 3.3V to 5.0V

– Down translation:

• 5.0V, 3.3V, 2.5V to 1.8V

• 5.0V, 3.3V to 2.5V

• 5.0V to 3.3V

• Up to 150Mbps with 5V or 3.3V VCC

• Supports standard function pinout

• Latch-up performance exceeds 250mA

per JESD 17

2 Applications

• Digital signage

• Controlling an indicator LED

• Increase the number of outputs on a

microcontroller

3 Description

The SN74LV8T594 device contains an 8-bit, serialin,

parallel-out shift register. Each parallel output of

the shift register is fed through a storage register

before reaching the primary device outputs (QA

through QH). Separate clocks (SRCLK and RCLK)

and direct overriding clear (SRCLR and RCLR) inputs

are provided for both the shift and storage registers,

allowing for loading data separately from sending it to

the outputs. Additionally, the last output of the internal

shift register is sent directly to the output QH' providing

a method to daisy-chain multiple shift registers.

The input is designed with a reduced threshold circuit

to support up translation when the supply voltage

is larger than the input voltage. Additionally, the 5V

tolerant input pins enable down translation when the

input voltage is larger than the supply voltage. The

output level is always referenced to the supply voltage

(VCC) and supports 1.8V, 2.5V, 3.3V, and 5V CMOS

levels.