1 Features

• FMCW transceiver

– Integrated PLL, transmitter, receiver, baseband

and ADC

– 76GHz to 81GHz coverage with 5GHz available

bandwidth

– 4 receive and 4 transmit channels

• AWR2944P: PCB interface to antennas

• AWR2E44P: Launch-on-Package (LOP)

interface to antennas

– Per transmit phase shifter

– Ultra-accurate chirp engine based on fractional-

N PLL

– TX power

• AWR2944P: 14dBm

• AWR2E44P: 13.5dBm

– RX noise figure

• AWR2944P: 10.5dB

• AWR2E44P: 11dB

– Phase noise at 1MHz

• VCO1: -96dBc/Hz (76 to 77GHz)

• VCO2: -95dBc/Hz (76 to 81GHz)

• Processing elements

– Arm® Cortex-R5F® core (supports lock step

operation) @400MHz

– TI digital signal processor C66x @450MHz

– TI radar hardware accelerator (HWA2.1) for

operations like FFT, log magnitude, and

memory compression

– Multiple EDMA instances for data movement

– Programmable embedded hardware security

module (HSM) using Arm®Cortex-M4

– Second Arm® Cortex M4 core for the DSS

(DSP Subsystem), controlling and configuring

the HWA2.1

• Functional safety compliant targeted

– Developed for functional safety applications

– Documentation will be available to aid ISO

26262 functional safety system design

– Hardware integrity up to ASIL B targeted

• Other interfaces available to user application

– Up to 9 ADC channels based on device variant

– 2 SPIs

– 4 UARTs

– I2C

– GPIOs

– 3 EPWMs

– 4-lane Aurora LVDS interface for raw ADC data

and debug instrumentation

– CSI2 Rx for playback of captured data

• On-Chip RAM

– 4.5Mbytes of ‘On Chip’ RAM

– Memory space split between DSP, MCU, and

shared L3

• Host interface

– 2x CAN-FD

– 10/100/1000Mbps Ethernet

• Supports a serial flash memory interface (loading

user application from QSPI flash memory)

• Device security (on select part numbers)

– Secure authenticated and encrypted boot

support

– Customer programmable root keys, symmetric

keys (256 bit), asymmetric keys (up to RSA-4K

or ECC-512) with key revocation capability

– Cryptographic hardware accelerators: PKA with

ECC, AES (up to 256 bit), SHA (up to 512 bit),

TRNG/DRBG, and SM2, SM3, SM4 (Chinese

crypto algorithms)

• Built-in firmware (ROM) and Self-calibrating

system across process and temperature

• AEC-Q100 targeted

• Advanced features

– Embedded self-monitoring with no external

processor involvement

– Embedded interference detection capability

• Power management

– On-die LDO network for enhanced PSRR

– LVCMOS IO supports dual voltage 3.3V and

1.8V

• Clock source

– 50/40MHz crystal with internal oscillator

– Supports external oscillator at 50/40MHz

– Supports externally driven clock (square or sine

wave) at 50/40MHz

– 25MHz external clock to eliminate external

crystal oscillator for Ethernet PHY when using

the 50MHz clock.

• Optimal Power Management Solution

– Recommended LP87745-Q1 Power

Management ICs (PMIC)

• Companion PMIC specially designed to

meet device power supply requirements

• Flexible mapping and factory programmed

configurations to support different use cases

• Cost-reduced hardware design using 0.65mm

pitch FCCSP package

– AWR2944P: 12mm × 12mm

– AWR2E44P: 13.5mm × 12mm

• Supports automotive junction temperature

operating range of –40°C to 140°C

2 Applications

• Corner Radar

• Front and Rear Radar

• Lane change assist

• Blind spot detection

• Automatic emergency braking

• Adaptive cruise control

• Cross traffic alert

3 Description

The AWR2944P/AWR2E44P is a Performance expansion to the AWR2944 portfolio with enhanced RF and

compute performance to meet NCAP + Automated Driving requirements. The AWR2944P/AWR2E44P is also

a single-chip mmWave sensor composed of a FMCW transceiver, capable of operation in the 76- to 81-GHz

band, radar data processing elements, and peripherals for in-vehicle networking. The AWR2944P/AWR2E44P is

built with TI’s low-power 45-nm RFCMOS process with own recipes to enhance RF and compute performance

enabling unprecedented levels of integration in a small form factor and minimal BOM. The AWR2944P/

AWR2E44P is an ideal solution for low-power, self-monitored, ultra-accurate radar systems in the automotive

space.

The AWR2E44P variant provides customers with an innovative Launch on Package (LOP) antenna feature

which facilitates the attachment of antennas directly on to the package. LOP technology enables loss-less

transmission of signals from the AWR2E44P chip to the antenna via holes in the PCB & launches on the bottom

of the chip. The chip and antenna are directly soldered to the PCB enabling low cost PCB material to be used

instead of expensive high-frequency material.

TI’s low-power 45nm RFCMOS process enables a monolithic implementation of a 4 TX, 4 RX system

with integrated PLL, VCO, mixer, and baseband ADC. Integrated in the DSP subsystem (DSS), is TI's highperformance

C66x DSP for radar signal processing. The device includes a Radio Processor Subsystem (RSS),

which is responsible for radar front-end configuration, control, and calibration. Within the Main Subsystem

(MSS), the device implements a user-programmable Arm Cortex-R5F processor allowing for custom control

and automotive interface applications. The hardware accelerator block (HWA 2.1) supplements the DSS and

MSS by offloading common radar processing such as FFT, constant false alarm rate (CFAR), scaling, and

compression. This saves MIPS on the DSS and MSS, opening up resources for custom applications and

higher-level algorithms.

A Hardware Security Module (HSM) is also provisioned in the device (available for only secure part variants).

The HSM consists of a programmable Arm Cortex-M4 core and the necessary infrastructure to provide a secure

zone of operation within the device.

Simple programming model changes can enable a wide variety of sensor implementation (Short, Mid, Long) with

the possibility of dynamic reconfiguration for implementing a multimode sensor.

Additionally, the AWR2944P/AWR2E44P is provided as a complete platform solution including TI hardware and

software reference designs, software drivers, sample configurations, API guides, and user documentation.