Application Information

The TXMC639 is a standard single-width Switched

Mezzanine Card (XMC) compatible module providing

a user configurable FPAG (AMD KintexTM 7) with up

to 16 differential ADC input channels and up to 8

single ended DAC output channels.

The TXMC639 ADC input channels are based on the

Octal 16-Bit 1.5Msps Differential LTC2320-16 ADC.

The TXMC639-11R provides 16, the TXMC639-10R

8 ADC channels. Each channel has a resolution of 16

bit and can operate at up to 1.5 Msps. The analog

input circuit is designed to configurable differential

input voltages ranges of ±20.57 V, ±10.28 V or ±5.14

V.

The TXMC639 DAC output channels are based on

the Dual 16bit AD5547 DAC. The TXMC639-11R

provides 8, the TXMC639-10R 4 DAC channels. Each

DAC output is designed as a configurable singleended

bipolar analog output. Output voltage is

configurable as ±10.0 V, ±5.0 V or ±2.5 V.

32 ESD-protected TTL lines provide a flexible digital

interface. All I/O lines are individually programmable

either as input or output. Input I/O lines are tri-stated

and could be used with the on-board pull up or as tristated

output. Each TTL I/O line has a pull resistor

sourced by a common pull voltage. The pull voltage

level is selectable to be either +3.3 V, +5.0 V or GND.

16 of these ESD-protected TTL lines can be switched

between TTL interface and RS422 interface.

Switching is done via the Board Configuration

Controller (BCC). All 8 RS422 transceivers have

individual internal switchable terminations.

For customer specific I/O extension or inter-board

communication, the TXMC639 provides 64 FPGA

I/Os on P14 and 4 FPGA Multi-Gigabit-Transceiver

on P16. P14 I/O lines can be configured as 64 single

ended LVCMOS25 or as 32 differential LVDS25

interface in accordance with TEWS CMC modules.

The User FPGA is connected to a 1GB, 32 bit wide

DDR3L SDRAM. The SDRAM-interface uses an

internal Memory Controller and is routed to a HP bank

of User FPGA KintexTM 7.

The TXMC639 is delivered with an FPGA Board

Reference Design (BRD). This is the standard

content of the serial configuration SPI flash, and is

loaded into the user FPGA by default after power up.

The User FPGA can also be configured via the onboard

Board Configuration Controller (BCC) or via

JTAG interface using a AMD programmer. For full

PCIe specification compliance the AMD Tandem

Configuration Feature is supported. The SPI flash

device is in-system programmable. Also an in-circuit

debugging option is available via a JTAG header for

real-time debugging of the User FPGA design.

User applications for the TXMC639 with KintexTM 7

FPGA can be developed using the design software

Vivado Design Suite. A full (non-webpack) license for

the Vivado Design Suite design tool is required, due

to FPGA density.