5-V, LOW POWER, 14-BIT, 200-KSPS SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO-POWER DOWN

FEATURES 200-KSPS Sampling Rate Built-In Conversion Clock INL: ±1 LSB Max DNL: ±1 LSB Max SINAD = 81.5 dB, SFDR = 95 dB THD = 94 dB at 15 kHz fin, 200 KSPS SPI/DSP-Compatible Serial Interfaces With SCLK Input up to 15 MHz Single 5-V Supply Rail-to-Rail Analog Input With 500 kHz BW Two I

14 位 200KSPS ADC，串行输出、自动断电和伪差动输入

The TLC3541 and TLC3545 are a family of high performance, 14-bit, low power, miniature CMOS analog-to-digital converters (ADCs). These devices operate from a single 5-V supply. Devices are available with single, dual, or single pseudo-differential inputs. All of these devices have a chip select (CS) • 200-KSPS Sampling Rate\n• Built-In Conversion Clock\n• INL: ±1 LSB Max DNL: ±1 LSB Max\n• SINAD = 81.5 dB, SFDR = 95 dB THD = 94 dB at 15 kHz fin, 200 KSPS\n• SPI/DSP-Compatible Serial Interfaces With SCLK Input up to 15 MHz\n• Single 5-V Supply\n• Rail-to-Rail Analog Input With 500 kHz BW\n• Two ;

200-KSPS Sampling Rate Built-In Conversion Clock

文件：837.17 Kbytes Page：27 Pages

5-V. LOW POWER, 14-BIT, 200-KSPS SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO-POWER DOWN

文件：481.82 Kbytes Page：23 Pages

丝印代码：3545I；5-V, LOW POWER, 14-BIT, 200-KSPS SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO-POWER DOWN

FEATURES 200-KSPS Sampling Rate Built-In Conversion Clock INL: ±1 LSB Max DNL: ±1 LSB Max SINAD = 81.5 dB, SFDR = 95 dB THD = 94 dB at 15 kHz fin, 200 KSPS SPI/DSP-Compatible Serial Interfaces With SCLK Input up to 15 MHz Single 5-V Supply Rail-to-Rail Analog Input With 500 kHz BW Two I

丝印代码：3545I；5-V, LOW POWER, 14-BIT, 200-KSPS SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO-POWER DOWN

FEATURES 200-KSPS Sampling Rate Built-In Conversion Clock INL: ±1 LSB Max DNL: ±1 LSB Max SINAD = 81.5 dB, SFDR = 95 dB THD = 94 dB at 15 kHz fin, 200 KSPS SPI/DSP-Compatible Serial Interfaces With SCLK Input up to 15 MHz Single 5-V Supply Rail-to-Rail Analog Input With 500 kHz BW Two I

丝印代码：AMM；5-V, LOW POWER, 14-BIT, 200-KSPS SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO-POWER DOWN

FEATURES 200-KSPS Sampling Rate Built-In Conversion Clock INL: ±1 LSB Max DNL: ±1 LSB Max SINAD = 81.5 dB, SFDR = 95 dB THD = 94 dB at 15 kHz fin, 200 KSPS SPI/DSP-Compatible Serial Interfaces With SCLK Input up to 15 MHz Single 5-V Supply Rail-to-Rail Analog Input With 500 kHz BW Two I

丝印代码：AMM；5-V, LOW POWER, 14-BIT, 200-KSPS SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO-POWER DOWN

FEATURES 200-KSPS Sampling Rate Built-In Conversion Clock INL: ±1 LSB Max DNL: ±1 LSB Max SINAD = 81.5 dB, SFDR = 95 dB THD = 94 dB at 15 kHz fin, 200 KSPS SPI/DSP-Compatible Serial Interfaces With SCLK Input up to 15 MHz Single 5-V Supply Rail-to-Rail Analog Input With 500 kHz BW Two I

丝印代码：3545I；5-V, LOW POWER, 14-BIT, 200-KSPS SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO-POWER DOWN

FEATURES 200-KSPS Sampling Rate Built-In Conversion Clock INL: ±1 LSB Max DNL: ±1 LSB Max SINAD = 81.5 dB, SFDR = 95 dB THD = 94 dB at 15 kHz fin, 200 KSPS SPI/DSP-Compatible Serial Interfaces With SCLK Input up to 15 MHz Single 5-V Supply Rail-to-Rail Analog Input With 500 kHz BW Two I

丝印代码：3545I；5-V, LOW POWER, 14-BIT, 200-KSPS SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO-POWER DOWN

FEATURES 200-KSPS Sampling Rate Built-In Conversion Clock INL: ±1 LSB Max DNL: ±1 LSB Max SINAD = 81.5 dB, SFDR = 95 dB THD = 94 dB at 15 kHz fin, 200 KSPS SPI/DSP-Compatible Serial Interfaces With SCLK Input up to 15 MHz Single 5-V Supply Rail-to-Rail Analog Input With 500 kHz BW Two I

200-KSPS Sampling Rate Built-In Conversion Clock

文件：837.17 Kbytes Page：27 Pages

200-KSPS Sampling Rate Built-In Conversion Clock

文件：837.17 Kbytes Page：27 Pages

5-V. LOW POWER, 14-BIT, 200-KSPS SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO-POWER DOWN

文件：481.82 Kbytes Page：23 Pages

封装/外壳：8-SOIC（0.154"，3.90mm 宽） 包装：管件 描述：IC ADC 14BIT SAR 8SOIC 集成电路（IC） 模数转换器（ADC）

200-KSPS Sampling Rate Built-In Conversion Clock

文件：837.17 Kbytes Page：27 Pages

5-V. LOW POWER, 14-BIT, 200-KSPS SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO-POWER DOWN

文件：481.82 Kbytes Page：23 Pages

封装/外壳：8-TSSOP，8-MSOP（0.118"，3.00mm 宽） 包装：管件 描述：IC ADC 14BIT SAR 8VSSOP 集成电路（IC） 模数转换器（ADC）

200-KSPS Sampling Rate Built-In Conversion Clock

文件：837.17 Kbytes Page：27 Pages

200-KSPS Sampling Rate Built-In Conversion Clock

文件：837.17 Kbytes Page：27 Pages

5-V. LOW POWER, 14-BIT, 200-KSPS SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO-POWER DOWN

文件：481.82 Kbytes Page：23 Pages

5-V. LOW POWER, 14-BIT, 200-KSPS SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO-POWER DOWN

文件：481.82 Kbytes Page：23 Pages

5-V. LOW POWER, 14-BIT, 200-KSPS SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO-POWER DOWN

文件：481.82 Kbytes Page：23 Pages

200-KSPS Sampling Rate Built-In Conversion Clock

文件：837.17 Kbytes Page：27 Pages

5-V. LOW POWER, 14-BIT, 200-KSPS SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO-POWER DOWN

文件：481.82 Kbytes Page：23 Pages

200-KSPS Sampling Rate Built-In Conversion Clock

文件：837.17 Kbytes Page：27 Pages

N-Channel Depletion-Mode Vertical DMOS FETs

Advanced DMOS Technology These depletion-mode (normally-on) transistors utilize an advanced vertical DMOS structure and Supertex’s well-proven silicon-gate manufacturing process. This combination produces devices with the power handling capabilities of bipolar transistors and with the high input

N-Channel Depletion-Mode Vertical DMOS FETs

Advanced DMOS Technology These depletion-mode (normally-on) transistors utilize an advanced vertical DMOS structure and Supertex’s well-proven silicon-gate manufacturing process. This combination produces devices with the power handling capabilities of bipolar transistors and with the high input

UNIVERSAL SINK DRIVER

文件：124.58 Kbytes Page：9 Pages

Fully integrated DECT transceiver

文件：116.73 Kbytes Page：28 Pages

Fully integrated DECT transceiver

文件：116.73 Kbytes Page：28 Pages