165-MHz C-STABLE HIGH-SPEED AMPLIFIERS

C-Stable Amplifiers Drive Any Capacitive Load High Speed − 165 MHz Bandwidth (−3 dB); CL = 0 pF − 100 MHz Bandwidth (−3 dB); CL = 100 pF − 35 MHz Bandwidth (−3 dB); CL = 1000 pF − 400 V/μs Slew Rate Unity Gain Stable High Output Drive, IO = 100 mA (typ) Very Low Distortion − THD = −75 dB

165-MHz C-STABLE HIGH-SPEED AMPLIFIERS

文件：479.03 Kbytes Page：28 Pages

165-MHz C-STABLE HIGH-SPEED AMPLIFIER

文件：1.0408 Mbytes Page：34 Pages

165-MHz C-STABLE HIGH-SPEED AMPLIFIERS

C-Stable Amplifiers Drive Any Capacitive Load High Speed − 165 MHz Bandwidth (−3 dB); CL = 0 pF − 100 MHz Bandwidth (−3 dB); CL = 100 pF − 35 MHz Bandwidth (−3 dB); CL = 1000 pF − 400 V/μs Slew Rate Unity Gain Stable High Output Drive, IO = 100 mA (typ) Very Low Distortion − THD = −75 dB

165-MHz C-STABLE HIGH-SPEED AMPLIFIERS

文件：479.03 Kbytes Page：28 Pages

165-MHz C-STABLE HIGH-SPEED AMPLIFIER

文件：1.0408 Mbytes Page：34 Pages

Quadruple D-latch

DESCRIPTION The HEF4042B is a 4-bit latch with four data inputs (D0 to D3), four buffered latch outputs (O0 to O3), four buffered complementary latch outputs (O0 to O3) and two common enable inputs (E0 and E1). Information on D0 to D3 is transferred to O0 to O3 while both E0 and E1 are in the sam

Quad D latch

The BU4042B is a four-circuit D latch with a common clock line and separate data input terminals. When the polarity input is set to “H”, input (D) is presented to output (Q) as is, as long as the clock input is rising, and when the clock input falls, output (Q) holds input (D) at that point. Whil

Diffused Red and Green Indicator LED - 18mm Round

文件：1.1486 Mbytes Page：2 Pages

RF Filter

文件：198.71 Kbytes Page：3 Pages

Wide Selection of Panel Seal Boots

文件：84.84 Kbytes Page：1 Pages