12-BIT, 2 ANALOG INPUT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER

FEATURES Simultaneous Sampling of 2 Single-Ended Signals or 1 Differential Signal Signal-to-Noise Ratio: 68 dB at fI = 2 MHz Differential Nonlinearity Error: ±1 LSB Integral Nonlinearity Error: ±1.5 LSB Auto-Scan Mode for 2 Inputs 3-V or 5-V Digital Interface Compatible Low Power: 218 mW M

双通道、DSP/uP 接口、信道自动扫描、低功耗、12 位、8MSPS ADC

The THS1209 is a CMOS, low-power, 12-bit, 8 MSPS analog-to-digital converter (ADC). The speed, resolution, bandwidth, and single-supply operation are suited for applications in radar, imaging, high-speed acquisition, and communications. A multistage pipelined architecture with output error correctio • Simultaneous Sampling of 2 Single-Ended Signals or 1 Differential Signal\n• Signal-to-Noise Ratio: 68 dB at fI = 2 MHz\n• Differential Nonlinearity Error: ±1 LSB\n• Integral Nonlinearity Error: ±1.5 LSB\n• Auto-Scan Mode for 2 Inputs\n• 3-V or 5-V Digital Interface Compatible\n• Low Power: 218 mW ;

12-BIT, 2 ANALOG INPUT, 8MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER

文件：318.35 Kbytes Page：33 Pages

丝印代码：THS1209I；12-BIT, 2 ANALOG INPUT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER

FEATURES Simultaneous Sampling of 2 Single-Ended Signals or 1 Differential Signal Signal-to-Noise Ratio: 68 dB at fI = 2 MHz Differential Nonlinearity Error: ±1 LSB Integral Nonlinearity Error: ±1.5 LSB Auto-Scan Mode for 2 Inputs 3-V or 5-V Digital Interface Compatible Low Power: 218 mW M

丝印代码：THS1209I；12-BIT, 2 ANALOG INPUT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER

FEATURES Simultaneous Sampling of 2 Single-Ended Signals or 1 Differential Signal Signal-to-Noise Ratio: 68 dB at fI = 2 MHz Differential Nonlinearity Error: ±1 LSB Integral Nonlinearity Error: ±1.5 LSB Auto-Scan Mode for 2 Inputs 3-V or 5-V Digital Interface Compatible Low Power: 218 mW M

12-BIT, 2 ANALOG INPUT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER

FEATURES Simultaneous Sampling of 2 Single-Ended Signals or 1 Differential Signal Signal-to-Noise Ratio: 68 dB at fI = 2 MHz Differential Nonlinearity Error: ±1 LSB Integral Nonlinearity Error: ±1.5 LSB Auto-Scan Mode for 2 Inputs 3-V or 5-V Digital Interface Compatible Low Power: 218 mW M

12-BIT, 2 ANALOG INPUT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER

文件：327.01 Kbytes Page：34 Pages

封装/外壳：32-TSSOP（0.240"，6.10mm 宽） 包装：管件 描述：IC ADC 12BIT PIPELINED 32TSSOP 集成电路（IC） 模数转换器（ADC）

封装/外壳：32-TSSOP（0.240"，6.10mm 宽） 包装：卷带（TR） 描述：IC ADC 12BIT PIPELINED 32TSSOP 集成电路（IC） 模数转换器（ADC）

12-BIT, 2 ANALOG INPUT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER

文件：327.01 Kbytes Page：34 Pages

PATENTED GOLD METALIZED SILICON GATE ENHANCEMENT MODE RF POWER VDMOS TRANSISTOR?

General Description Silicon VDMOS and LDMOS transistors designed specifically for broadband RF applications. Suitable for Military Radios, Cellular and Paging Amplifier Base Stations, Broadcast FM/AM, MRI, Laser Driver and others. Polyfet process features gold metal for greatly extended lifetime

42-Bit Vacuum Fluorescent Display Tube Driver with Digital Dimming Function

GENERAL DESCRIPTION The MSC1209 is a Bi-CMOS display driver for a 1/2-duty vacuum fluorescent display tube. The MSC1209 consists of an 84-bit shift register, an 84-bit latch circuit, a 10-bit digital dimming circuit, 42-bit segment drivers, a 2-bit grid circuit, and a cascade control circuit. Th

CCD LINEAR IMAGE SENSOR

CCD LINEAR IMAGE SENSOR CCD (Charge Coupled Device) The TCD1209D is a high speed and low dark current 2048 elements CCD image sensor. The sensor is designed for facsimile, imagescanner and OCR. The device contains a row of 2048 elements photodiodes which provide a 8 lines / mm (200 DP

1A ULTRA LOW DROPOUT POSITIVE ADJUSTABLE & FIXED REGULATOR

DESCRIPTION The US1206 family of devices are ultra low dropout 1A regulators using PNP transistor as the pass element. These products are ideal when a single input supply is available only and the dropout voltage is less than 1V, exceeding the minimum dropout characteristics of NPN/PNP hybrid reg

12-Bit, uP Compatible, Double-Buffered D to A Converters

文件：361.79 Kbytes Page：18 Pages