SNUBBERLESS TRIACS

DESCRIPTION The T4016xKS series of isolated triacs uses a high performance MESA GLASS technology. The SNUBBERLESSTM concept offersuppression of RC network and it is suitable for application such as phase control and static switching on in ductive or resistive load. FEATURES ■ IT(RMS)

SNUBBERLESS TRIACS

DESCRIPTION The T4016xKS series of isolated triacs uses a high performance MESA GLASS technology. The SNUBBERLESSTM concept offersuppression of RC network and it is suitable for application such as phase control and static switching on in ductive or resistive load. FEATURES ■ IT(RMS)

Quad Analog Switch/Quad Multiplexer

The MC14016B quad bilateral switch is constructed with MOS P–channel and N–channel enhancement mode devices in a single monolithic structure. Each MC14016B consists of four independent switches capable of controlling either digital or analog signals. The quad bilateral switch is used in signal gat

Quad bilateral switches

GENERAL DESCRIPTION The 74HC/HCT4016 are high-speed Si-gate CMOS devices and are pin compatible with the “4016” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT4016 have four independent analog switches (transmission gates). FEATURES •

Quadruple bilateral switches

DESCRIPTION The HEF4016B has four independent analogue switches (transmission gates). Each switch has two input/output terminals (Y/Z) and an active HIGH enable input (E). When E is connected to VDD a low impedance bidirectional path between Y and Z is established (ON condition). When E is connec

Quadruple bilateral switches

DESCRIPTION The HEF4016B has four independent analogue switches (transmission gates). Each switch has two input/output terminals (Y/Z) and an active HIGH enable input (E). When E is connected to VDD a low impedance bidirectional path between Y and Z is established (ON condition). When E is connec

Quadruple bilateral switches

DESCRIPTION The HEF4016B has four independent analogue switches (transmission gates). Each switch has two input/output terminals (Y/Z) and an active HIGH enable input (E). When E is connected to VDD a low impedance bidirectional path between Y and Z is established (ON condition). When E is connec