Features

 Includes ST state-of-the-art patented

technology

 Radio

– 2.4 GHz

– RF transceiver supporting Bluetooth® 5.2

specification

– RX sensitivity: -95.5 dBm (Bluetooth® Low

Energy at 1 Mbps)

– Programmable output power up to +4 dBm

with 1 dB steps

– Integrated balun to reduce BOM

– Support for 1 Mbps

– Dedicated Arm® 32-bit Cortex® M0+ CPU

for real-time Radio layer

– Accurate RSSI to enable power control

– Suitable for systems requiring compliance

with radio frequency regulations ETSI EN

300 328, EN 300 440, FCC CFR47 Part 15

and ARIB STD-T66

– Support for external PA

– Available integrated passive device (IPD)

companion chip for optimized matching

solution (MLPF-WB-01E3)

 Ultra-low-power platform

– 2.0 to 3.6 V power supply

– – 10 °C to +85 °C temperature range

– 18 nA shutdown mode

– 700 nA Standby mode + RTC + 48 KB

RAM

– Radio: Rx 7.7 mA / Tx at 0 dBm 8.6 mA

 Core: Arm® 32-bit Cortex®-M4 CPU with FPU,

adaptive real-time accelerator (ART

Accelerator) allowing 0-wait-state execution

from Flash memory, frequency up to 64 MHz,

MPU, 80 DMIPS and DSP instructions

 Performance benchmark

– 1.25 DMIPS/MHz (Drystone 2.1)

 Supply and reset management

– Ultra-safe, low-power BOR (brownout

reset) with five selectable thresholds

– Ultra-low-power POR/PDR

– Programmable voltage detector (PVD)

– VBAT mode with RTC and backup registers

 Clock sources

– 32 MHz crystal oscillator with integrated

trimming capacitors (Radio and CPU clock)

– 32 kHz crystal oscillator for RTC (LSE)

– Internal low-power 32 kHz RC (LSI1)

– Internal low-drift 32 kHz (stability

±500 ppm) RC (LSI2)

– Internal multispeed 100 kHz to 48 MHz

oscillator, factory-trimmed

– High speed internal 16 MHz factory

trimmed RC (±1%)

– 1x PLL for system clock and ADC

 Memories

– 320 KB Flash memory with sector

protection (PCROP) against R/W

operations, enabling radio stack and

application

– 48 KB SRAM, including 36 KB with

hardware parity check

– 20x32-bit backup register

– Boot loader supporting USART, SPI, I2C

interfaces

– 1 Kbyte (128 double words) OTP

 Rich analog peripherals (down to 2.0 V)

– 12-bit ADC 2.5 Msps, 190 µA/Msps

 System peripherals

– Inter processor communication controller

(IPCC) for communication with Bluetooth®

Low Energy

– HW semaphores for resources sharing

between CPUs

– 1x DMA controller (7x channels) supporting

ADC, SPI, I2C, USART, AES, timers

– 1x USART (ISO 7816, IrDA, SPI Master,

Modbus and Smartcard mode)

– 1x SPI 32 Mbit/s

– 1x I2C (SMBus/PMBus)

– Touch sensing controller, up to eight

sensors

– 1x 16-bit, four channels advanced timer

– 1x 32-bit, four channels timer

– 2x 16-bit ultra-low-power timer

– 1x independent Systick

– 1x independent watchdog

– 1x window watchdog

 Security and ID

– Secure firmware installation (SFI) for

Bluetooth® Low Energy SW stack

– 2x hardware encryption AES maximum

256-bit for the application and the

Bluetooth® Low Energy

– HW public key authority (PKA)

– Cryptographic algorithms: RSA,

Diffie-Helman, ECC over GF(p)

– True random number generator (RNG)

– Sector protection against R/W operation

(PCROP)

– CRC calculation unit

– Die information: 96-bit unique ID

– IEEE 64-bit unique ID. Possibility to derive

Bluetooth® Low Energy 48-bit EUI

 Up to 30 fast I/Os, 28 of them 5 V-tolerant

 Development support

– Serial wire debug (SWD), JTAG for the

application processor

– Application cross trigger

 Package is ECOPACK2 compliant