DESCRIPTION

The STLVDS3486, is a differential line receiver that implements the electrical characteristics of low voltage differential signaling (LVDS). This signaling technique lowers the output voltage levels of 5V differential standard levels (such as TIA/EIA-422B) to reduce the power, increase the switching speeds and allow operations with a 3.3V supply rail. This differential receiver provides a valid logical output state with a 3.3V supply rail. It also provides a valid logical output state with a ±100mV differential input voltage within the input common mode voltage range. The input common mode voltage allows 1V of ground potential difference between two LVDS nodes.

■ MEETS OR EXCEEDS THE REQUIREMENTS OF ANSI TIA/EIA-644 STANDARD

■ OPERATES WITH A SINGLE 3.3V SUPPLY

■ DESIGNED FOR SIGNALING RATE UP TO 400Mbps

■ DIFFERENTIAL INPUT THRESHOLDS ±100mV MAX

■ TYPICAL PROPAGATION DELAY TIME OF 2.5ns

■ POWER DISSIPATION 60mW TYPICAL PER RECEIVER AT 200MHz

■ LOW VOLATGE TTL (LVTTL) LOGIC OUTPUT LEVELS

■ PIN COMPATIBLE WITH THE MC3486 AND SN65LVD3486

■ OPEN CIRCUIT FAIL SAFE

■ ESD PROTECTION:

7KV RECEIVER PINS

3KV ALL PINS VS GND