■ High Performance 16-bit CPU

● CPU Frequency: 0 to 50 MHz

● 40ns instruction cycle time at 50-MHz CPU clock

● 4-stage pipeline

● Register-based design with multiple variable register banks

● Enhanced boolean bit manipulation facilities

● Additional instructions to support HLL and operating systems

● Single-cycle context switching support

● 1024 bytes on-Chip special function register area

■ Memory Organisation

● 1KByte on-chip RAM

● Up to 16 MBytes linear address space for code and data (1 MByte with SSP used)

■ External Memory Interface

● Programmable external bus characteristics for different address ranges

● 8-bit or 16-bit external data bus

● Multiplexed or demultiplexed external address/data buses

● Five programmable chip-select signals

● Hold and hold-acknowledge bus arbitration support

■ One Channel PWM Unit

■ Fail Safe Protection

● Programmable watchdog timer

● Oscillator Watchdog

■ Interrupt

● 8-channel interrupt-driven single-cycle data transfer facilities via peripheral event controller (PEC)

● 16-priority-level interrupt system with 17 sources, sample-rate down to 40 ns

■ Timers

● Two multi-functional general purpose timer units with 5 timers

● Clock Generation via on-chip PLL, or via direct or prescaled clock input

■ Serial Channels

● Synchronous/asynchronous

● High-speed-synchronous serial port SSP

■ Up to 77 general purpose I/O lines

■ No bootstrap loader

■ Electrical Characteristics

● 5V Tolerant I/Os

● 5V Fail-Safe Inputs (Port 5)

● Power: 3.3 Volt +/-0.3V

● Idle and power down modes

■ Support

● C-compilers, macro-assembler packages, emulators, evaluation boards, HLL debuggers, simulators, logic analyser disassemblers, programming boards

■ Package

● 100-Pin Thin Quad Flat Pack (TQFP)