GENERAL DISCRIPTION

The CB35000 standard cell series uses a high performance, low voltage, triple level metal, HCMOS5S 0.5 micron process to achieve subnanosecond internal speeds while offering very low power dissipation and high noise immunity.

With an average gate density of 5500 gates/mm2, the CB35000 family allows the design of highly complex devices. The potential available gate count ranges above 1.5 Million equivalent gates. Devices can operate over a Vdd voltage range of 2.7 to 3.6 volts.

The I/O count for this array family ranges to over 600 signals and 800 pins dependent upon the package technology utilized. A Sea of I/O approach has been followed to give a solution to today’s problems of drive levels and specialized interface standards. The technology does not utilize a set bond pad spacing but allows for pad spacings from 80 microns upwards. The I/O is fully compatible with that of the ISB35000 Structured Array family.

FEATURES

■ 0.5 micron triple layer metal HCMOS5S process featuring retrograde well technology, low resistance salicided active areas, polysilicide gates and thin metal oxide.

■ 3.3 V optimized transistor with 5 V I/O inter face capability

■ 2 - input NAND delay of 210 ps (typ) with fanout = 2.

■ Broad I/O functionality including LVCMOS, LVTTL, GTL, PECL, and LVDS.

■ High drive I/O; capability of sinking up to 48 mA with slew rate control, current spike suppression and impedance matching.

■ Generators to support SPRAM, DPRAM, ROM and MULT with BIST options.

■ Extensive embedded function library includ ing DSP and ST micros, popular third party micros and Synopsys synthetic libraries.

■ Fully independent power and ground config urations for inputs, core and outputs.

■ I/O ring capability up to 800 pads.

■ Output buffers capable of driving ISA, EISA, PCI, MCA, and SCSI interface levels.

■ Active pull up and pull down devices.

■ Buskeeper I/O functions.

■ Oscillators for wide frequency spectrum.

■ Broad range of 300 SSI cells.

■ Low Power / Low Drive library subset.

■ Design For Test includes IEEE 1149.1 JTAG Boundary Scan architecture built in.

■ Cadence and Mentor based design system with interfaces from multiple workstations.

■ Broad ceramic and plastic package range.

■ Latchup trigger current > +/- 500 mA. ESD protection > +/- 4000 volts.