GENERAL DESCRIPTION

The LPC47N252 is a 208-pin 3.3V LPC-based ACPI 1.1 and PC99/PC2001 compliant Notebook I/O Controller with Fast Infrared for mobile applications.

FEATURES

■ 3.3V Operation with 5V Tolerant Buffers

■ ACPI 1.1, PC99/PC2001 Compliant

■ LPC Interface with Clock Run Support

− Serial IRQ Interface Compatible with Serialized IRQ Support for PCI Systems

− 15 Direct IRQs

− Four 8-Bit DMA Channels

− ACPI SCI Interface

− nSMI

− Shadowed write only registers

■ Internal 64K Flash ROM

− Programmed From Direct Parallel Interface, 8051, or LPC Host

− 2k-Byte Lockable Boot Block

− Can be Programmed Without 8051 Intervention

■ Three Power Planes

− Low Standby Current in Sleep Mode

− Intelligent Auto Power Management for Super I/O

■ ACPI Embedded Controller Interface

■ Configuration Register Set Compatible with ISA Plug-and-Play Standard (Version 1.0a)

■ High-Performance Embedded 8051 Keyboard and System Controller

− Provides System Power Management

− System Watch Dog Timer (WDT)

− 8042 Style Host Interface

− Supports Interrupt and Polling Access

− 256 Bytes Data RAM

− On-Chip Memory-Mapped Control Registers

− Access to RTC and CMOS Registers

− Up to 16x8 Keyboard Scan Matrix

− Two 16 Bit Timer/Counters

− Integrated Full-Duplex Serial Port Interface

− Eleven 8051 Interrupt Sources

− Thirty-Two 8-Bit, Host/8051 Mailbox Registers

− Thirty-six Maskable Hardware Wake-Up Events

− Fast GATEA20

− Fast CPU_RESET

− Multiple Clock Sources and Operating Frequencies

− IDLE and SLEEP Modes

− Fail-Safe Ring Oscillator

■ Advanced Infrared Communications Controller (IrCC 2.0)

− IrDA V1.2 (4Mbps), HPSIR, ASKIR, Consumer IR Support

− Two IR Ports

− Relocatable Base I/O Address

■ Real-Time Clock

− MC146818 and DS1287 Compatible

− 256 Bytes of Battery Backed CMOS in Two 128-Byte Banks

− 128 Bytes of CMOS RAM Lockable in 4x32 Byte Blocks

− 12 and 24 Hour Time Format

− Binary and BCD Format

− <2µA Standby Current (typ)

■ Two 8584-Style ACCESS.Bus Controllers

− 8051 Controlled Logic Allows ACCESS.Bus Master or Slave Operation

− ACCESS.Bus Controllers are Fully Operational on Standby Power

− 2 Sets of Dedicated Pins per ACCESS.Bus Controller

■ Four independent Hardware Driven PS/2 Ports

■ 83 General Purpose I/O Pins

− 36 Maskable Hardware Wake-Event Capable

− 18 Programmable Open-Drain/Push-Pull Outputs

− 16 Mapped into 8051 SFR Space

− 24 LPC/8051-Addressable

■ Three Programmable Pulse-Width Modulator Outputs

− Independent Clock Rates

− 6 Bit Duty Cycle Granularity

− VCC1 and VCC2 operation mode

■ Dual Fan Tachometer Inputs

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