Applications

 2-stage InGaP power amplifier designed for 2.4 to 2.5 GHz ISM,

IEEE 802.11b, 802.11g WLAN and ZigBee band applications

Features

 2.4 to 2.5 GHz operation

 WLAN/ZigBee® applications

 Advanced GaAs HBT process

 Integrated output power detector and F2 filter

 Low voltage positive bias supply (3.3 V)

 Low quiescent current: 50 mA

 27 dB small signal gain

 802.11g linear power: +18 dBm (includes integrated filter loss)

 802.11b mask-compliant power: +21 dBm (includes integrated

filter loss)

 802.15.4 mask-compliant power: +15.4 dBm (includes

integrated filter loss)

 Low-cost 16-pin QFN (3 x 3 x 0.75 mm) plastic package

 Lead (Pb)-free, and RoHS-compliant

Description

The SKY65006-348LF-348LF is a linear, high-gain two-stage

power amplifier with integrated output power detector and second

harmonic (F2) filter, designed for low voltage operations. This

device is manufactured on an advanced Gallium Arsenide (GaAs),

Heterojunction Bipolar Transistor (HBT) process. The device is

designed for power amplifier applications in WLAN, ZigBee, and

spread spectrum systems from 2.4 to 2.5 GHz. The amplifier is

packaged in a QFN-16, 3 x 3 x 0.75 mm package.

The Skyworks SKY65006-348LF is a high-performance 2-stage

InGaP power amplifier designed for 2.4 to 2.5 GHz ISM,

IEEE 802.11b, 802.11g WLAN and ZigBee band applications. The

SKY65006-348LF is a high-efficiency linear amplifier designed for

single 3.3 V supply operation, requiring no input and output

matching components for 50 Ω operation. This device also

includes an internal power detector and integrated harmonic filter

for reduced PC board component count. The integrated low pass

filter is also highly effective in reducing harmonics at their source

by localizing harmonic rejection to a tiny portion of the PA chip.

This significantly reduces the risk of radiation from a high order

filter design external to the amplifier. Filtering of harmonics in this

way can eliminate the need for an external shield over the PA, and

reduces overall cost.

A functional block diagram is provided in Figure 1. The pin

configuration and package are shown in Figure 2. Signal pin

assignments and functional pin descriptions are provided in

Table 1.