Applications

 Simultaneous voice and LTE systems

 Diversity antenna switching

Features

 Single control voltage input

 Broadband frequency range: 0.4 to 3.0 GHz

 Low insertion loss: 0.5 dB @ 2.2 GHz

 No DC blocking capacitors required

 Positive control voltage range: 1.35 to 3.1 V

 GSM power handling

 Small QFN (12-pin, 2 x 2 mm) package

(MSL1, 260 C per JEDEC J-STD-020)

Description

The SKY13396-397LF is a state-of-the-art CMOS, Silicon-On-

Insulator (SOI) double-pole, double-throw (DPDT) switch. The

switch provides high-linearity performance, low insertion loss,

and high isolation.

Switching is controlled by one voltage input (CTRL1). Depending

on the logic voltage level applied to this pin, the PORT1 and

PORT2 pins connect to one of the two other RF port pins (PORT3

or PORT4) through a low insertion loss path, while maintaining a

high isolation path to the alternate port. No external DC blocking

capacitors are required on the RF path as long as no DC voltage is

applied externally.

The SKY13396-397LF DPDT switch is provided in a compact

Quad Flat No-Lead (QFN) 2 x 2 mm package. A functional block

diagram is shown in Figure 1. The pin configuration and package

are shown in Figure 2. Signal pin assignments and functional pin

descriptions are provided in Table 1.