KEY FEATURES

• Three independent DSPLLs in a single

monolithic IC supporting flexible SyncE/

IEEE 1588 and SETS architectures

• Ultra-low jitter of 95 fs

• Enhanced hitless switching minimizes

output phase transients

• Input frequency range:

• External crystal: 48 to 54 MHz

• REF clock: 5 to 250 MHz

• Diff clock: 8 kHz to 750 MHz

• LVCMOS clock: 8 kHz to 250 MHz

• Output frequency range:

• Differential: 1 PPS to 718.5 MHz

• LVCMOS: 1 PPS to 250 MHz

• Meets the requirements of:

• ITU-T G.8262 (SyncE) EEC Options 1

and 2

• ITU-T G.812 Type III, IV

• ITU-T G.813 Option 1

• Telcordia GR-1244, GR-253

(Stratum-3/3E)