Features

 Fifteen 0.7 V low-power, pushpull

HCSL PCIe Gen3 outputs

 100 MHz /133 MHz PLL

operation, supports PCIe and

QPI

 PLL bandwidth SW SMBUS

programming overrides the latch

value from HW pin

 9 selectable SMBUS addresses

 SMBus address configurable to

allow multiple buffers in a single

control network 3.3 V supply

voltage operation

 Separate VDDIO for outputs

 PLL or bypass mode

 Spread spectrum tolerable

 1.05 to 3.3 V I/O supply voltage

 50 ps output-to-output skew

 50 ps cyc-cyc jitter (PLL mode)

 Low phase jitter (Intel QPI, PCIe

Gen 1/2/3/4 common clock

compliant)

 Gen 3 SRNS Compliant

 100 ps input-to-output delay

 Extended Temperature:

–40 to 85 °C

 64-pin QFN