Features

 Nineteen 0.7 V current-mode,

HCSL PCIe Gen 3 outputs

 100 MHz /133 MHz PLL

operation, supports PCIe and

QPI

 PLL bandwidth SW SMBUS

programming overrides the latch

value from HW pin

 9 selectable SMBus addresses

 Fixed external feedback path

 8 dedicated OE pin

 PLL or bypass mode

 Spread spectrum tolerable

 50 ps output-to-output skew

 Fixed 0 ps input to output delay

 Low phase jitter (Intel QPI, PCIe

Gen 1/Gen 2/Gen 3/Gen 4

common clock compliant

 Gen 3 SRNS Compliant

 100 ps input-to-output delay

 Extended Temperature:

–40 to 85 °C

 Package: 72-pin QFN