General Description

The SDA 525x contains a slicer for TTX, VPS and WSS, an accelerating acquisition hardware modul, a display generator for “Level 1” TTX data and an 8 bit microcontroller running at 333 ns cycle time. The controller with dedicated hardware guarantees flexibility, does most of the internal processing of TTX acquisition, transfers data to/from the external memory interface and receives/transmits data via I2C and UART user interfaces. The block diagram shows the internal organization of the SDA 525x. The Slicer combined with dedicated hardware stores TTX data in a VBI buffer of 1 Kbyte. The microcontroller firmware does the total acquisition task (hamming- and parity-checks, page search and evaluation of header control bits) once per field.

Features

Acquisition

• Feature selection via special function register

• Simultaneous reception of TTX, VPS and WSS

• Fixed framing code for VPS and TTX

• Acquisition during VBI

• Direct access to VBI RAM buffer

• Acquisition of packets X/26, X/27, 8/30 (firmware)

• Assistance of all relevant checks (firmware)

• 1-bit framing code error tolerance (switchable)

Display

• Features selectable via special function register

• 50/60 Hz display

• Level 1 serial attribute display pages

• Blanking and contrast reduction output

• 8 direct addressable display pages for SDA 5250, SDA 5254 and SDA 5255

• 1 direct addressable display page for SDA 5251 and SDA 5252

• 12 × 10 character matrix

• 96 character ROM (standard G0 character set)

• 143 national option characters for 11 languages

• 288 characters for X/26 display

• 64 block mosaic graphic characters

• 32 characters for OSD in expanded character ROM + 32 characters inside OSD box

• Conceal/reveal

• Transparent foreground/background - inside/outside of a box

• Contrast reduction inside/outside of a box

• Cursor (colour changes from foreground to background colour)

• Flash (flash rate 1s)

• Programmable horizontal and vertical sync delay

• Full screen background colour in outer screen

• Double size / double width / double height characters

Synchronization

• Display synchronization to sandcastle or Horizontal Sync (HS) and Vertical Sync (VS) with start-stop-oscillator

• Independent clock systems for acquisition, display and controller

Microcontroller

• 8 bit C500-CPU (8051 compatible)

• 18 MHz internal clock

• 0.33 µs instruction cycle

• Parallel 8-bit data and 16...19 - bit address bus (ROMless-Version)

• Eight 16-bit data pointer registers (DPTR)

• Two 16-bit timers

• Watchdog timer

• Capture compare timer for infrared remote control decoding

• Serial interface (UART)

• 256 bytes on-chip RAM

• 8 Kbyte on-chip display-RAM (access via MOVX) for SDA 5250, SDA 5254 and SDA 5255

• 1 Kbyte on-chip display-RAM (access via MOVX) for SDA 5251 and SDA 5252

• 1 Kbyte on-chip TVT/VPS-Acquisition-buffer-RAM (access via MOVX)

• 1 Kbyte on-chip extended-RAM (access via MOVX) for SDA 5250, SDA 5254 and SDA 5255

• 6 channel 8-bit pulse width modulation unit

• 2 channel 14-bit pulse width modulation unit

• 4 multiplexed ADC inputs with 8-bit resolution

• One 8-bit I/O port with open drain output and optional I2C-Bus emulation (PORT 0)

• Two 8-bit multifunctional I/O ports (PORT 1, PORT 3)

• One 4-bit port working as digital or analog inputs (PORT 2)

• One 2-bit I/O port with optional functions

• One 3-bit I/O port with optional RAM/ROM address expansion up to 512 Kbyte (ROMless-Version)

– P-SDIP-52-1 Package or P-MQFP-64-1 for ROM-Versions (SDA 5251, SDA 5252, SDA 5254, SDA 5255)

– P-MQFP-80-1 Package for ROMless-Version (SDA 5250 M)

– P-LCC-84-2 Package for Emulator-Version (SDA 5250)

– 5 V Supply Voltage