The HYB 514405BJ is the new generation dynamic RAM organized as 1 048 576 words by 4-bit. The HYB 514405BJ utilizes CMOS silicon gate process as well as advances circuit techniques to provide wide operation margins, both internally and for the system user. Multiplexed address inputs permit the HYB 514405BJ to be packed in a standard plastic P-SOJ-26/20 package. This package size provides high system bit densities and is compatible with commonly used automatic testing and insertion equipment. System oriented feature include single + 5 V (± 10 ) power supply, direct interfacing with high performance logic device families.

Preliminary Information

• 1 048 576 words by 4-bit organization

• 0 to 70 ˚C operating temperature

• Hyper Page Mode - EDO

• Performance:

• Single + 5 V (± 10 ) supply

• Low power dissipation

max. 660 mW active (-50 version)

max. 605 mW active (-60 version)

max. 550 mW active (-70 version)

• Standby power dissipation:

11 mW max.standby (TTL)

5.5 mW max.standby (CMOS)

1.1 mW max.standby (CMOS) for Low Power Version

• Read, write, read-modify write, CAS-before-RAS refresh, RAS-only refresh, hidden refresh and test mode capability

• All inputs and outputs TTL-compatible

• 1024 refresh cycles / 16 ms

• 1024 refresh cycles / 128 ms for Low Power Version

• Plastic Packages: P-SOJ-26/20-5 with 300 mil width