64 MBit Synchronous DRAM

• High Performance:

• Fully Synchronous to Positive Clock Edge

• 0 to 70°C operating temperature

• Four Banks controlled by BA0 & BA1

• Programmable CASLatency: 2 & 3

• Programmable Wrap Sequence: Sequential or Interleave

• Programmable Burst Length: 1, 2, 4, 8

• full page (optional) for sequential wrap around

• Multiple Burst Read with Single Write Operation

• Automatic and Controlled Precharge Command

• Data Mask for Read / Write control (x4, x8)

• Data Mask for byte control (x16)

• Auto Refresh (CBR) and Self Refresh

• Suspend Mode and Power Down Mode

• 4096 refresh cycles / 64 ms

• Random Column Address every CLK ( 1-N Rule)

• Single 3.3V +/- 0.3V Power Supply

• LVTTL Interface version

• Plastic Packages: P-TSOPII-54 400mil width (x4, x8, x16)

• -8 version for PC100 2-2-2 applications

-8B version for PC100 3-2-3 applications