This device is a 64 MBit dynamic RAM organized 4 194 304 x 16 bits. The device is fabricated on an advanced first generation 64Mbit 0,35 µm CMOS silicon gate process technology.

Advanced Information

• 4 194 304 words by 16-bit organization

• 0 to 70 °C operating temperature

• Hyper Page Mode - EDO - operation

• Performance:

• Single + 3.3 V (± 0.3V) power supply

• Low power dissipation:

7.2 mW standby (TTL)

3.24 mW standby (MOS)

720 µA standby for L-version

• Read, write, read-modify-write, CAS-before-RAS refresh (CBR), RAS-only refresh, hidden refresh and Self Refresh (L-version only

• 2 CAS / 1 WE byte control

• 8192 refresh cycles/128 ms , 13 R/ 9C addresses (HYB 3164165AT)

4096 refresh cycles/ 64 ms , 12 R/ 10C addresses (HYB 3165165AT)

2048 refresh cycles/ 32 ms , 11 R/ 11C addresses (HYB 3166165AT)

• 256ms refresh period for L-versions

• Plastic Package: P-TSOPII-50 400 mil