Key Features

• JEDEC standard 1.35V(1.28V~1.45V) & 1.5V(1.425V~1.575V) Power Supply

• VDDQ = 1.35V(1.28V~1.45V) & 1.5V(1.425V~1.575V)

• 400MHz fCK for 800Mb/sec/pin, 533MHz fCK for 1066Mb/sec/pin, 667MHz fCK for 1333Mb/sec/pin, 800MHz fCK for 1600Mb/sec/pin

• 8 independent internal bank

• Programmable CAS Latency: 6,7,8,9,10,11

• Programmable Additive Latency(Posted CAS) : 0, CL - 2, or CL - 1 clock

• Programmable CAS Write Latency(CWL) = 5(DDR3-800), 6(DDR3-1066), 7(DDR3-1333) and 8(DDR3-1600)

• 8-bit pre-fetch

• Burst Length: 8 (Interleave without any limit, sequential with starting address “000” only), 4 with tCCD = 4 which does not allow seamless read or write [either On the fly using A12 or MRS]

• Bi-directional Differential Data Strobe

• Internal(self) calibration : Internal self calibration through ZQ pin (RZQ : 240 ohm ± 1)

• On Die Termination using ODT pin

• Average Refresh Period 7.8us at lower then TCASE 85°C, 3.9us at 85°C < TCASE ≤ 95°C

• Asynchronous Reset